class SparseVec[A <: Data] extends Record
A sparse vector. Under the hood, this is a Record that can be dynamically indexed as if it were a dense Vec.
SparseVec has the usual trappings of a Vec. It has a size
and a
gen
type. However, it also has an indices
argument. This indicates the
indices at which the SparseVec is allowed to have data. Additionally,
the behavior of a SparseVec around what happens if a value is read from
a value not in the indices
:
- defaultValue
sets the default value that is read from an index between
the zeroth index and the largest value in indices
that is not in the
indices
.
- outOfBoundsValue
sets the behavior when reading a value larger than the
largest value in indices
.
The reason for this configurability is to enable exact compatibility with an equivalent dense Vec of the same size and initialized to a given value. Specifically, use SparseVec.DefaultValueBehavior.DynamicIndexEquivalent and SparseVec.OutOfBoundsBehavior.First to make this behave as such:
1. The SparseVec has a default value of how a FIRRTL compiler compiles DontCare for a dynamic index.
2. The SparseVec out-of-bounds behavior returns the zeroth element if a zeroth element exists. Otherwise, it returns a DontCare.
Note that this DontCare is likely not a true "don't care" that will be optimized to any value. Instead, it is a value equal to how a FIRRTL compiler chooses to optimize a dynamic index into a wire vector initialized with a DontCare. This has historically been zero.
Once created, a SparseVec can be written or read from as a Record. It may also be read from using a dynamic index, but not written to. Neither the default value nor the out-of-bounds value may be written to. The dynamic index type is conifgurable and may be one of:
- SparseVec.Lookup.Binary to convert the SparseVec index into a binary index into a dense vector. - SparseVec.Lookup.OneHot to convert the SparseVec index into a one-hot encoded index into a dense vector using Mux1H. - SparseVec.Lookup.IfElse to use a sequence of when statements.
A SparseVec will take up storage equal to the size of the provided mapping argument with one additional slot for the default value, if one is needed.
- Source
- SparseVec.scala
- Grouped
- Alphabetic
- By Inheritance
- SparseVec
- Record
- Aggregate
- Data
- SourceInfoDoc
- NamedComponent
- HasId
- InstanceId
- AnyRef
- Any
- by AsReadOnly
- by DataEquality
- by toConnectableDefault
- by ConnectableDefault
- by any2stringadd
- by StringFormat
- by Ensuring
- by ArrowAssoc
- Hide All
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- Public
- Protected
connection
- final def :#=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "mono-direction connection operator", aka the "coercion operator".
The "mono-direction connection operator", aka the "coercion operator".
For
consumer :#= producer
, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '#' means to ignore flips, always drive from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes: - Connecting two
util.DecoupledIO
's would connectbits
,valid
, ANDready
from producer to consumer (despiteready
being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=- producer
the right-hand-side of the connection, all members will be driving, none will be driven-to
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :#=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "mono-direction connection operator", aka the "coercion operator".
The "mono-direction connection operator", aka the "coercion operator".
For
consumer :#= producer
, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '#' means to ignore flips, always drive from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes: - Connecting two
util.DecoupledIO
's would connectbits
,valid
, ANDready
from producer to consumer (despiteready
being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=- producer
the right-hand-side of the connection, all members will be driving, none will be driven-to
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :#=[S <: Data](lProducer: => S)(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "mono-direction connection operator", aka the "coercion operator".
The "mono-direction connection operator", aka the "coercion operator".
For
consumer :#= producer
, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '#' means to ignore flips, always drive from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes: - Connecting two
util.DecoupledIO
's would connectbits
,valid
, ANDready
from producer to consumer (despiteready
being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "aligned connection operator" between a producer and consumer.
The "aligned connection operator" between a producer and consumer.
For
consumer :<= producer
, each ofconsumer
's leaf members which are aligned with respect toconsumer
are driven from the correspondingproducer
leaf member. Onlyconsumer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectbits
andvalid
from producer to consumer, but leaveready
unconnected
- producer
the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "aligned connection operator" between a producer and consumer.
The "aligned connection operator" between a producer and consumer.
For
consumer :<= producer
, each ofconsumer
's leaf members which are aligned with respect toconsumer
are driven from the correspondingproducer
leaf member. Onlyconsumer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectbits
andvalid
from producer to consumer, but leaveready
unconnected
- producer
the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<=[S <: Data](lProducer: => S)(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "aligned connection operator" between a producer and consumer.
The "aligned connection operator" between a producer and consumer.
For
consumer :<= producer
, each ofconsumer
's leaf members which are aligned with respect toconsumer
are driven from the correspondingproducer
leaf member. Onlyconsumer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectbits
andvalid
from producer to consumer, but leaveready
unconnected
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "bi-direction connection operator", aka the "tur-duck-en operator"
The "bi-direction connection operator", aka the "tur-duck-en operator"
For
consumer :<>= producer
, both producer and consumer leafs could be driving or be driven-to. Theconsumer
's members aligned w.r.t.consumer
will be driven by corresponding members ofproducer
; theproducer
's members flipped w.r.t.producer
will be driven by corresponding members ofconsumer
Identical to calling
:<=
and:>=
in sequence (order is irrelevant), e.g.consumer :<= producer
thenconsumer :>= producer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
- An additional type restriction is that all relative orientations of
consumer
andproducer
must match exactly.
Additional notes:
- Connecting two wires of
util.DecoupledIO
chisel type would connectbits
andvalid
from producer to consumer, andready
from consumer to producer. - If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
- "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken;
:<>=
is a:=
stuffed with a<>
- producer
the right-hand-side of the connection
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "bi-direction connection operator", aka the "tur-duck-en operator"
The "bi-direction connection operator", aka the "tur-duck-en operator"
For
consumer :<>= producer
, both producer and consumer leafs could be driving or be driven-to. Theconsumer
's members aligned w.r.t.consumer
will be driven by corresponding members ofproducer
; theproducer
's members flipped w.r.t.producer
will be driven by corresponding members ofconsumer
Identical to calling
:<=
and:>=
in sequence (order is irrelevant), e.g.consumer :<= producer
thenconsumer :>= producer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
- An additional type restriction is that all relative orientations of
consumer
andproducer
must match exactly.
Additional notes:
- Connecting two wires of
util.DecoupledIO
chisel type would connectbits
andvalid
from producer to consumer, andready
from consumer to producer. - If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
- "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken;
:<>=
is a:=
stuffed with a<>
- producer
the right-hand-side of the connection
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<>=[S <: Data](lProducer: => S)(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "bi-direction connection operator", aka the "tur-duck-en operator"
The "bi-direction connection operator", aka the "tur-duck-en operator"
For
consumer :<>= producer
, both producer and consumer leafs could be driving or be driven-to. Theconsumer
's members aligned w.r.t.consumer
will be driven by corresponding members ofproducer
; theproducer
's members flipped w.r.t.producer
will be driven by corresponding members ofconsumer
Identical to calling
:<=
and:>=
in sequence (order is irrelevant), e.g.consumer :<= producer
thenconsumer :>= producer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
- An additional type restriction is that all relative orientations of
consumer
andproducer
must match exactly.
Additional notes:
- Connecting two wires of
util.DecoupledIO
chisel type would connectbits
andvalid
from producer to consumer, andready
from consumer to producer. - If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
- "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken;
:<>=
is a:=
stuffed with a<>
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :=(that: => Data)(implicit sourceInfo: SourceInfo): Unit
The "strong connect" operator.
The "strong connect" operator.
For chisel3._, this operator is mono-directioned; all sub-elements of
this
will be driven by sub-elements ofthat
.- Equivalent to
this :#= that
For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=
- Equivalent to
this :<>= that
- that
the Data to connect from
- Definition Classes
- Data
- Equivalent to
- final def :>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
For
consumer :>= producer
, each ofproducer
's leaf members which are flipped with respect toproducer
are driven from the corresponding consumer leaf member Onlyproducer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectready
from consumer to producer, but leavebits
andvalid
unconnected
- producer
the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
For
consumer :>= producer
, each ofproducer
's leaf members which are flipped with respect toproducer
are driven from the corresponding consumer leaf member Onlyproducer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectready
from consumer to producer, but leavebits
andvalid
unconnected
- producer
the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :>=[S <: Data](lProducer: => S)(implicit evidence: =:=[SparseVec[A], S], sourceInfo: SourceInfo): Unit
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
For
consumer :>= producer
, each ofproducer
's leaf members which are flipped with respect toproducer
are driven from the corresponding consumer leaf member Onlyproducer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectready
from consumer to producer, but leavebits
andvalid
unconnected
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectableDefault[SparseVec[A]] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def <>(that: => Data)(implicit sourceInfo: SourceInfo): Unit
The "bulk connect operator", assigning elements in this Vec from elements in a Vec.
The "bulk connect operator", assigning elements in this Vec from elements in a Vec.
For chisel3._, uses the
chisel3.internal.BiConnect
algorithm; sub-elements of thatmay end up driving sub-elements of
this- Complicated semantics, hard to write quickly, will likely be deprecated in the future
For Chisel._, emits the FIRRTL.<- operator
- Equivalent to
this :<>= that
without the restrictions that bundle field names and vector sizes must match
- that
the Data to connect from
- Definition Classes
- Data
Ungrouped
- def ===(rhs: SparseVec[A]): Bool
Dynamic recursive equality operator for generic Data
Dynamic recursive equality operator for generic Data
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toDataEquality[SparseVec[A]] performed by method DataEquality in chisel3.Data.
- Definition Classes
- DataEquality
- Exceptions thrown
ChiselException
whenlhs
andrhs
are different types during elaboration time
- def apply(addr: UInt, lookupType: Type = Lookup.Binary)(implicit sourceinfo: SourceInfo): A
Read a value from a SparseVec using one of several possible lookup types.
Read a value from a SparseVec using one of several possible lookup types. The returned value is read-only.
- addr
the address of the value to read from the vec
- lookupType
the type of lookup, e.g., binary, one-hot, or when-based
- sourceinfo
implicit source locator information
- returns
a read-only value from the specified address
- Exceptions thrown
ChiselException
if the returned value is written to
- def as[S <: Data](implicit ev: <:<[SparseVec[A], S]): connectable.Connectable[S]
Static cast to a super type
Static cast to a super type
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- macro def asTypeOf[T <: Data](that: T): T
Does a reinterpret cast of the bits in this node into the format that provides.
Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.
x.asTypeOf(that) performs the inverse operation of x := that.toBits.
- Definition Classes
- Data
- Note
bit widths are NOT checked, may pad or drop bits from input
,that should have known widths
- final macro def asUInt: UInt
Reinterpret cast to UInt.
Reinterpret cast to UInt.
- Definition Classes
- Data
- Note
value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7
,Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.
- def autoSeed(name: String): SparseVec.this.type
Takes the last seed suggested.
Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).
If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.
Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.
- returns
this object
- Definition Classes
- Data → HasId
- val base: SparseVec[A]
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def circuitName: String
- Definition Classes
- HasId
- def className: String
Name for Pretty Printing
Name for Pretty Printing
- Definition Classes
- Record
- def cloneType: SparseVec.this.type
Internal API; Chisel users should look at chisel3.chiselTypeOf(...).
- def containsAFlipped: Boolean
- final val elements: VectorMap[String, A]
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- def exclude(members: (SparseVec[A]) => Data*): connectable.Connectable[SparseVec[A]]
Select members of base to exclude
Select members of base to exclude
- members
functions given the base return a member to exclude
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def exclude: connectable.Connectable[SparseVec[A]]
Adds base to excludes
Adds base to excludes
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def excludeAs[S <: Data](members: (SparseVec[A]) => Data*)(implicit ev: <:<[SparseVec[A], S]): connectable.Connectable[S]
Select members of base to exclude and static cast to a new type
Select members of base to exclude and static cast to a new type
- members
functions given the base return a member to exclude
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def excludeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[SparseVec[A], S]): connectable.Connectable[S]
Programmatically select members of base to exclude and static cast to a new type
Programmatically select members of base to exclude and static cast to a new type
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def excludeProbes: connectable.Connectable[SparseVec[A]]
Exclude probes
Exclude probes
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def getElements: Seq[Data]
Returns a Seq of the immediate contents of this Aggregate, in order.
- final def getWidth: Int
Returns the width, in bits, if currently known.
Returns the width, in bits, if currently known.
- Definition Classes
- Data
- def hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
- Definition Classes
- HasId → InstanceId
- def isLit: Boolean
- Definition Classes
- Data
- final def isWidthKnown: Boolean
Returns whether the width is currently known.
Returns whether the width is currently known.
- Definition Classes
- Data
- def litOption: Option[BigInt]
Return an Aggregate's literal value if it is a literal, None otherwise.
Return an Aggregate's literal value if it is a literal, None otherwise. If any element of the aggregate is not a literal (or DontCare), the result isn't a literal.
- returns
an Aggregate's literal value if it is a literal, None otherwise.
- def litValue: BigInt
Return an Aggregate's literal value if it is a literal, otherwise an exception is thrown.
- def notWaivedOrSqueezedOrExcluded: Boolean
True if no members are waived or squeezed or excluded
True if no members are waived or squeezed or excluded
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def readOnly(implicit sourceInfo: SourceInfo): SparseVec[A]
Returns a read-only view of this Data
Returns a read-only view of this Data
It is illegal to connect to the return value of this method. This Data this method is called on must be a hardware type.
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toAsReadOnly[SparseVec[A]] performed by method AsReadOnly in chisel3.Data.
- Definition Classes
- AsReadOnly
- def squeeze(members: (SparseVec[A]) => Data*): connectable.Connectable[SparseVec[A]]
Select members of base to squeeze
Select members of base to squeeze
- members
functions given the base return a member to squeeze
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def squeeze: connectable.Connectable[SparseVec[A]]
Adds base to squeezes
Adds base to squeezes
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def squeezeAll: connectable.Connectable[SparseVec[A]]
Squeeze all members of base
Squeeze all members of base
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def squeezeAllAs[S <: Data](implicit ev: <:<[SparseVec[A], S]): connectable.Connectable[S]
Squeeze all members of base and upcast to super type
Squeeze all members of base and upcast to super type
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def squeezeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]]): connectable.Connectable[SparseVec[A]]
Programmatically select members of base to squeeze
Programmatically select members of base to squeeze
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def suggestName(seed: => String): SparseVec.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than
autoSeed
, in that regardless of whetherautoSeed
was called, suggestName will always take precedence.- seed
The seed for the name of this component
- returns
this object
- Definition Classes
- HasId
- final def toAbsoluteTarget: ReferenceTarget
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
- Definition Classes
- NamedComponent → InstanceId
- final def toNamed: ComponentName
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
- Definition Classes
- NamedComponent → InstanceId
- Note
Should not be called until circuit elaboration is complete
- def toPrintable: Printable
Default "pretty-print" implementation Analogous to printing a Map Results in "
$className(elt0.name -> elt0.value, ...)
" - final def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget
Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.
Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.
If
root
is defined, the target is a hierarchical path starting fromroot
.If
root
is not defined, the target is a hierarchical path equivalent totoAbsoluteTarget
.- Definition Classes
- NamedComponent
- Note
If
,root
is defined, and has not finished elaboration, this must be called withinatModuleBodyEnd
.The NamedComponent must be a descendant of
,root
, if it is defined.This doesn't have special handling for Views.
- def toString(): String
The collection of chisel3.Data
The collection of chisel3.Data
This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to
Vec
). For example:// Assume we have some type MyRecord that creates a Record from the ListMap val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W))) // "buzz" is higher order because it was added later than "fizz" record("fizz") := "hdead".U record("buzz") := "hbeef".U val uint = record.asUInt assert(uint === "hbeefdead".U) // This will pass
- Definition Classes
- Record → AnyRef → Any
- final def toTarget: ReferenceTarget
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
- Definition Classes
- NamedComponent → InstanceId
- Note
Should not be called until circuit elaboration is complete
- def typeName: String
A non-ambiguous name of this
Data
for use in generated Verilog namesA non-ambiguous name of this
Data
for use in generated Verilog names- Definition Classes
- Data
- def unsafe: connectable.Connectable[Data]
Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members
Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waive(members: (SparseVec[A]) => Data*): connectable.Connectable[SparseVec[A]]
Select members of base to waive
Select members of base to waive
- members
functions given the base return a member to waive
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveAll: connectable.Connectable[SparseVec[A]]
Waive all members of base
Waive all members of base
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveAllAs[S <: Data](implicit ev: <:<[SparseVec[A], S]): connectable.Connectable[S]
Waive all members of base and static cast to a new type
Waive all members of base and static cast to a new type
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveAs[S <: Data](members: (SparseVec[A]) => Data*)(implicit ev: <:<[SparseVec[A], S]): connectable.Connectable[S]
Select members of base to waive and static cast to a new type
Select members of base to waive and static cast to a new type
- members
functions given the base return a member to waive
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[SparseVec[A], S]): connectable.Connectable[S]
Programmatically select members of base to waive and static cast to a new type
Programmatically select members of base to waive and static cast to a new type
- Implicit
- This member is added by an implicit conversion from SparseVec[A] toConnectable[SparseVec[A]] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- final def widthOption: Option[Int]
Returns Some(width) if the width is known, else None.
Returns Some(width) if the width is known, else None.
- Definition Classes
- Data
SourceInfoTransformMacro
These internal methods are not part of the public-facing API!
The equivalent public-facing methods do not have the do_
prefix or have the same name. Use and look at the
documentation for those. If you want left shift, use <<
, not do_<<
. If you want conversion to a
Seq of Bools look at the asBools
above, not the one below. Users can safely ignore
every method in this group!
🐉🐉🐉 Here be dragons... 🐉🐉🐉
These do_X
methods are used to enable both implicit passing of SourceInfo
while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your
designs, are converted to their "hidden", do_*
, via macro transformations. Without using macros here, only one
of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a
chained apply as an explicit 'implicit' argument and will throw type errors.
The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method
into a call to an internal, hidden do_*
that takes an explicit SourceInfo by inserting an
implicitly[SourceInfo]
as the explicit argument.
- def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo): T
- Definition Classes
- Data
- def do_asUInt(implicit sourceInfo: SourceInfo): UInt
- Definition Classes
- Data