Chisel Users Community
If you're a Chisel user and want to stay connected to the wider user community, any of the following are great avenues:
- Interact with other Chisel users in one of our Gitter chat rooms:
- Ask/Answer Questions on Stack Overflow using the
[chisel]tag - Ask questions and discuss ideas on the Chisel/FIRRTL Mailing Lists:
- Follow us on our
@chisel_langTwitter Account - Subscribe to our
chisel-langYouTube Channel
Projects Using Chisel/FIRRTL
If you want to add your project to the list, let us know on the Chisel users mailing list!
Chisel
| Project | Description | Author | Links |
|---|---|---|---|
| Rocket Chip Generator | RISC-V System-on-Chip Generator, 5-stage RISC-V Microprocessor | @ucb-bar, @sifive | Report |
| Berkeley Out-of-order Machine | RISC-V Out-of-order/Multi-issue Microprocessor | @ucb-bar | Site, Thesis |
| RISC-V Mini | 3-stage RISC-V Microprocessor | @ucb-bar | |
| Sodor Processor Collection | Educational RISC-V Microprocessors (1, 2, 3, 5-stage) | @ucb-bar | |
| Patmos | Time-predictable VLIW processor | @t-crest | Site |
| OpenSoC Fabric | Parametrizable Network-on-Chip Generator | @LBL-CoDEx | Site |
| Hwacha | Decoupled Vector-fetch Accelerator | @ucb-bar | Report |
| DANA | Multilayer Perceptron Accelerator for Rocket | @bu-icsg | Paper |
| Gemmini | Systolic-array Accelerator Generator | @ucb-bar | Paper |
| Edge TPU | AI Inference Accelerator | @google | Video |
| ChiselFlow | Information Flow Types in Chisel3 | @apl-cornell | Paper |
| PHMon | Programmable Hardware Monitor | @bu-icsg | Paper |
| DINO CPU | Davis In-Order (DINO) CPU models | @jlpteaching | Paper |
| Quasar | CHISEL implementation of SweRV-EL2 | @Lampro-Mellon | Video |
| FP Divider Pipelined / Not Pipelined | IEEE binary 32-bit divider using Harmonized Parabolic Synthesis | @Ssavas | Paper |
| Square Root Pipelined / Not Pipelined | Square Root using Harmonized Parabolic Synthesis | @Ssavas | Paper |
| Pillars | A Consistent CGRA Design Framework | @pku-dasys | Paper, Video |
| Tensil | Machine Learning Accelerators | @tensil-ai | Website |
| Twine | A Chisel Extension for Component-Level Heterogeneous Design | @shibo-chen | Paper |
| RISCVAssembler | A RISC-V assembler library for Scala/Chisel projects | @carlosedp | Site, Demo Site) |
| SoC-Now | A plug and play supported RISC-V System-on-Chip Generator, 5-stage RISC-V Microprocessor | @merledu | Site, Poster, Video |
Tooling
| Project | Destription | Author | Links |
|---|---|---|---|
| Tywaves (demo) | Type-based waveform viewer for Chisel | @rameloni | Chisel backend, Surfer-Tywaves fork |
FIRRTL
| Project | Description | Author | Links |
|---|---|---|---|
| MIDAS/DESSERT/Golden Gate | FPGA Accelerated Simulation | @ucb-bar | Papers 1, 2, 3, Video |
| Chiffre | Run-time Fault Injection | @IBM | Paper |
| SIRRTL | Security-typed FIRRTL | @apl-cornell | Paper |
| obfuscation | Transforms to Obfuscate FIRRTL Circuits | @jpsety | |
| Area/Timing Estimates | Transforms for Area and Timing Estimates | @intel | Video |
Chisel Developers Community
If you want to get more involved with the Chisel/FIRRTL ecosystem of projects, feel free to reach out to us on any of the mediums above. If you prefer to dive right in (or have bugs to report), a complete list of the associated Chisel/FIRRTL ecosystem of projects is below:
Contributors
Chisel, FIRRTL, and all related projects would not be possible without the contributions of our fantastic developer community. The following people have contributed to the current release of the projects:
@abejgonzalez@adkian-sifive@albert-magyar@albertchen-sifive@alonamid@aswaterman@azidar@AzureSkyResearch@Burnleydev1@bwrcbcr@carlosedp@ccelio@chick@chiselbot@colin4124@colinschmidt@danluu@David-Durst@davidbiancolin@debs-sifive@dependabot-preview[bot]@dependabot[bot]@diningyo@djmmoss@dobios@donggyukim@dt27182@dtzSiFive@ducky64@edcote@edwardcwang@ekiwi@ekiwi-sifive@england2233@eymay@felixonmars@ferresb@Gallagator@grebe@hcook@hngenc@huytbvo@ImeshBalasuriya@ingallsj@jackbackrack@jackkoenig@jackwdandrew@jared-barocsi@jascondley@jcmartin@jiegec@jimmysitu@JL102@johnsbrew@jyhi@kammoh@kasanovic@konda-x1@learning-chip@liuyic00@lizhirui@ljwljwljwljw@lsteveol@lu-ping@marmbrus@Martoni@michael-etzkorn@mikeurbach@mwachs5@NELEwb@nyuichi@oharboe@palmer-dabbelt@parzival3@pranith@ptorru@rachelzoll@Ravencus@richardxia@rupertlssmith@ryan-lund@sbeamer@scala-steward@schoeberl@sdtwigg@SebastianBoe@seldridge@sequencer@sgandham2@Shorla@shunshou@ShuyunJia@SihaoLiu@SingularityKChen@sinofp@sterin@stevobailey@terpstra@TsaiAnson@ucbjrl@vidhatre@wunderabt@yqszxx@yuchangyuan@yunsup@zhemao@zhongzc@zhutmost
Papers
While Chisel has come a long way since 2012, the original Chisel paper provides some background on motivations and an overview of the (now deprecated) Chisel 2 language:
The FIRRTL IR and FIRRTL compiler, introduced as part of Chisel 3, are discussed in both the following paper and specification1:
- Izraelevitz, Adam, et al. "Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations." Proceedings of the 36th International Conference on Computer-Aided Design. IEEE Press, 2017.
- Li, Patrick S., Adam M. Izraelevitz, and Jonathan Bachrach. "Specification for the FIRRTL Language." EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-9 (2016).
Finally, Chisel's functional programming and bit-width inference ideas were inspired by earlier work on a hardware description language called Gel:
Attribution
If you use Chisel in your research, consider citing:
@inproceedings{bachrach:2012:chisel,
author={J. {Bachrach} and H. {Vo} and B. {Richards} and Y. {Lee} and A. {Waterman} and R {Avižienis} and J. {Wawrzynek} and K. {Asanović}},
booktitle={DAC Design Automation Conference 2012},
title={Chisel: Constructing hardware in a Scala embedded language},
year={2012},
volume={},
number={},
pages={1212-1221},
keywords={application specific integrated circuits;C++ language;field programmable gate arrays;hardware description languages;Chisel;Scala embedded language;hardware construction language;hardware design abstraction;functional programming;type inference;high-speed C++-based cycle-accurate software simulator;low-level Verilog;FPGA;standard ASIC flow;Hardware;Hardware design languages;Generators;Registers;Wires;Vectors;Finite impulse response filter;CAD},
doi={10.1145/2228360.2228584},
ISSN={0738-100X},
month={June},}
If you use FIRRTL in your research consider citing:
@INPROCEEDINGS{8203780,
author={A. Izraelevitz and J. Koenig and P. Li and R. Lin and A. Wang and A. Magyar and D. Kim and C. Schmidt and C. Markley and J. Lawson and J. Bachrach},
booktitle={2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
title={Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks,
and transformations},
year={2017},
volume={},
number={},
pages={209-216},
keywords={field programmable gate arrays;hardware description languages;program compilers;software reusability;hardware development practices;hardware libraries;open-source hardware intermediate representation;hardware compiler transformations;Hardware construction languages;retargetable compilers;software development;virtual Cambrian explosion;hardware compiler frameworks;parameterized libraries;FIRRTL;FPGA mappings;Chisel;Flexible Intermediate Representation for RTL;Reusability;Hardware;Libraries;Hardware design languages;Field programmable gate arrays;Tools;Open source software;RTL;Design;FPGA;ASIC;Hardware;Modeling;Reusability;Hardware Design Language;Hardware Construction Language;Intermediate Representation;Compiler;Transformations;Chisel;FIRRTL},
doi={10.1109/ICCAD.2017.8203780},
ISSN={1558-2434},
month={Nov},}
@techreport{Li:EECS-2016-9,
Author = {Li, Patrick S. and Izraelevitz, Adam M. and Bachrach, Jonathan},
Title = {Specification for the FIRRTL Language},
Institution = {EECS Department, University of California, Berkeley},
Year = {2016},
Month = {Feb},
URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-9.html},
Number = {UCB/EECS-2016-9}
}