object BackendCompilationUtilities extends LazyLogging
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- @deprecated
- Deprecated
(Since version Chisel 6.7.0) This object hasn't been practical to use since Chisel 5.0.0. If you are doing compilation to Verilog use
circt.stage.ChiselStage. For simulation use ChiselSim.- Source
- BackendCompilationUtilities.scala
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Deprecated Value Members
- lazy val TestDirectory: File
Parent directory for tests
Parent directory for tests
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def copyResourceToFile(name: String, file: File): Unit
Copy the contents of a resource to a destination file.
Copy the contents of a resource to a destination file.
- name
the name of the resource
- file
the file to write it into
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def cppToExe(prefix: String, dir: File): ProcessBuilder
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def createTestDirectory(testName: String): File
Create a test directory
Create a test directory
Will create outer directory called testName then inner directory based on the current time
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String = ""): Boolean
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def executeExpectingSuccess(prefix: String, dir: File): Boolean
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder
compule chirrtl to verilog by using a separate process
compule chirrtl to verilog by using a separate process
- prefix
basename of the file
- dir
directory where file lives
- returns
true if compiler completed successfully
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def loggingProcessLogger: ProcessLogger
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def makeHarness(template: (String) => String, post: String)(f: File): File
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def timeStamp: String
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0
- def verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File, suppressVcd: Boolean = false, resourceFileName: String = firrtl.transforms.BlackBoxSourceHelper.defaultFileListName, extraCmdLineArgs: Seq[String] = Seq.empty): ProcessBuilder
Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.
Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.
The Verilator prefix will be V$dutFile, and running this will generate C++ sources and headers as well as a makefile to compile them.
Verilator will automatically locate the top-level module as the one among all the files which are not included elsewhere. If multiple ones exist, the compilation will fail.
If the file BlackBoxSourceHelper.fileListName (or an overridden .f resource filename that is specified with the optional resourceFileName parameter) exists in the output directory, it contains a list of source files to be included. Filter out any files in the vSources sequence that are in this file so we don't include the same file multiple times. This complication is an attempt to work-around the fact that clients used to have to explicitly include additional Verilog sources. Now, more of that is automatic.
- dutFile
name of the DUT .v without the .v extension
- dir
output directory
- vSources
list of additional Verilog sources to compile
- cppHarness
C++ testharness to compile/link against
- suppressVcd
specifies if VCD tracing should be suppressed
- resourceFileName
specifies what filename to look for to find a .f file
- extraCmdLineArgs
list of additional command line arguments
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.7.0) BackendCompilationUtilities will be removed in Chisel 7.0.0