Packages

p

svsim

package svsim

Ordering
  1. Alphabetic
Visibility
  1. Public
  2. Protected

Package Members

  1. package vcs
  2. package verilator

Type Members

  1. trait Backend extends AnyRef
  2. case class CommonCompilationSettings(verilogPreprocessorDefines: Seq[VerilogPreprocessorDefine] = Seq(), optimizationStyle: OptimizationStyle = CommonCompilationSettings.OptimizationStyle.Default, availableParallelism: AvailableParallelism = CommonCompilationSettings.AvailableParallelism.Default, defaultTimescale: Option[Timescale] = None, libraryExtensions: Option[Seq[String]] = None, libraryPaths: Option[Seq[String]] = None) extends Product with Serializable

    Settings supported by all svsim backends.

  3. case class ModuleInfo(name: String, ports: Seq[Port]) extends Product with Serializable
  4. final class Simulation extends AnyRef
  5. final class Workspace extends AnyRef

Value Members

  1. object Backend
  2. object CommonCompilationSettings extends Serializable
  3. object ModuleInfo extends Serializable
  4. object Simulation
  5. object Workspace

Ungrouped