case class CommonCompilationSettings(verilogPreprocessorDefines: Seq[VerilogPreprocessorDefine] = Seq(), optimizationStyle: OptimizationStyle = CommonCompilationSettings.OptimizationStyle.Default, availableParallelism: AvailableParallelism = CommonCompilationSettings.AvailableParallelism.Default, defaultTimescale: Option[Timescale] = None, libraryExtensions: Option[Seq[String]] = None, libraryPaths: Option[Seq[String]] = None, includeDirs: Option[Seq[String]] = None, fileFilter: PartialFunction[File, Boolean] = PartialFunction.empty, directoryFilter: PartialFunction[File, Boolean] = PartialFunction.empty, simulationSettings: CommonSimulationSettings = CommonSimulationSettings.default) extends Product with Serializable
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Inherited
- CommonCompilationSettings
- Serializable
- Product
- Equals
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Implicitly
- by any2stringadd
- by StringFormat
- by Ensuring
- by ArrowAssoc
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Visibility
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Instance Constructors
- new CommonCompilationSettings(verilogPreprocessorDefines: Seq[VerilogPreprocessorDefine] = Seq(), optimizationStyle: OptimizationStyle = CommonCompilationSettings.OptimizationStyle.Default, availableParallelism: AvailableParallelism = CommonCompilationSettings.AvailableParallelism.Default, defaultTimescale: Option[Timescale] = None, libraryExtensions: Option[Seq[String]] = None, libraryPaths: Option[Seq[String]] = None, includeDirs: Option[Seq[String]] = None, fileFilter: PartialFunction[File, Boolean] = PartialFunction.empty, directoryFilter: PartialFunction[File, Boolean] = PartialFunction.empty, simulationSettings: CommonSimulationSettings = CommonSimulationSettings.default)
Value Members
- val availableParallelism: AvailableParallelism
- val defaultTimescale: Option[Timescale]
- val directoryFilter: PartialFunction[File, Boolean]
- val fileFilter: PartialFunction[File, Boolean]
- val includeDirs: Option[Seq[String]]
- val libraryExtensions: Option[Seq[String]]
- val libraryPaths: Option[Seq[String]]
- val optimizationStyle: OptimizationStyle
- def productElementNames: Iterator[String]
- Definition Classes
- Product
- val simulationSettings: CommonSimulationSettings
- val verilogPreprocessorDefines: Seq[VerilogPreprocessorDefine]
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.