Decoders
It is common in a complex design to recognize certain patterns from a big UInt
coming from a data bus and dispatch
actions to next pipeline stage based on such observation. The circuit doing so can be called as 'decoders' such as
address decoders in a bus crossbar or instruction decoders in a CPU frontend. Chisel provides some utility class to
generate them in util.exprimental.decode
package.
Basic Decoders
The simplest API provided by decoder
is essentially just a TruthTable
encoding your desired input and output.
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
class SimpleDecoder extends Module {
val table = TruthTable(
Map(
BitPat("b001") -> BitPat("b?"),
BitPat("b010") -> BitPat("b?"),
BitPat("b100") -> BitPat("b1"),
BitPat("b101") -> BitPat("b1"),
BitPat("b111") -> BitPat("b1")
),
BitPat("b0"))
val input = IO(Input(UInt(3.W)))
val output = IO(Output(UInt(1.W)))
output := decoder(input, table)
}