Type Members

1.  class AddDedupGroupAnnotations extends Phase
2.  class AddImplicitOutputAnnotationFile extends Phase

   Adds an firrtl.options.OutputAnnotationFileAnnotation if one does not exist.

   Adds an firrtl.options.OutputAnnotationFileAnnotation if one does not exist. This replicates old behavior where an output annotation file was always written.

3.  class AddImplicitOutputFile extends Phase

   Add a output file for a Chisel circuit, derived from the top module in the circuit, if no ChiselOutputFileAnnotation already exists.

4.  class AddSerializationAnnotations extends Phase

   Adds stage.CircuitSerializationAnnotations based on ChiselOutputFileAnnotation

5.  class Checks extends Phase

   Sanity checks an firrtl.AnnotationSeq before running the main firrtl.options.Phases of chisel3.stage.ChiselStage.

6.  class Convert extends Phase

   This prepares a ChiselCircuitAnnotation for compilation with FIRRTL. This does three things:

   This prepares a ChiselCircuitAnnotation for compilation with FIRRTL. This does three things:

   • Uses chisel3.internal.firrtl.Converter to generate a FirrtlCircuitAnnotation
   • Extracts all firrtl.annotations.Annotations from the chisel3.internal.firrtl.Circuit
   • Generates any needed RunFirrtlTransformAnnotations from extracted firrtl.annotations.Annotations
7.  class Elaborate extends Phase

   Elaborate all chisel3.stage.ChiselGeneratorAnnotations into chisel3.stage.ChiselCircuitAnnotations.

8.  class Emitter extends Phase

   Emit a chisel3.stage.ChiselCircuitAnnotation to a file if a chisel3.stage.ChiselOutputFileAnnotation is present.

   Emit a chisel3.stage.ChiselCircuitAnnotation to a file if a chisel3.stage.ChiselOutputFileAnnotation is present.

   To do

   This should be switched to support correct emission of multiple circuits to multiple files.