Type Members

1.  sealed abstract class ActualDirection extends AnyRef

   Resolved directions for both leaf and container nodes, only visible after a node is bound (since higher-level specifications like Input and Output can override directions).

2.  sealed abstract class Aggregate extends Data

   An abstract class for data types that solely consist of (are an aggregate of) other Data objects.

3.  class AliasedAggregateFieldException extends ChiselException
4.  sealed class AsyncReset extends Element with Reset

   Data type representing asynchronous reset signals

   Data type representing asynchronous reset signals

   These signals are similar to Clocks in that they must be glitch-free for proper circuit operation. Regs defined with the implicit reset being an AsyncReset will be asychronously reset registers.

5.  class AutoClonetypeException extends ChiselException
6.  case class BiConnectException(message: String) extends ChiselException with Product with Serializable
7.  case class Binary(bits: Bits) extends FirrtlFormat with Product with Serializable

   Format bits as Binary

8.  class BindingException extends ChiselException
9.  sealed abstract class Bits extends Element with ToBoolable

   A data type for values represented by a single bitvector.

   A data type for values represented by a single bitvector. This provides basic bitwise operations.

10.  abstract class BlackBox extends BaseBlackBox

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

    Example:

    1. Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

       IBUFDS #(.DIFF_TERM("TRUE"),
                .IOSTANDARD("DEFAULT")) ibufds (
        .IB(ibufds_IB),
        .I(ibufds_I),
        .O(ibufds_O)
       );

       To instantiate it, a BlackBox can be used like following:

       import chisel3._
       import chisel3.experimental._
       
       // Example with Xilinx differential buffer IBUFDS
       class IBUFDS extends BlackBox(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                         "IOSTANDARD" -> "DEFAULT"
                            )) {
         val io = IO(new Bundle {
           val O = Output(Clock()) // IO names will be the same
           val I = Input(Clock())  // (without 'io_' in prefix)
           val IB = Input(Clock()) //
         })
       }

    Note

    The parameters API is experimental and may change

11.  sealed class Bool extends UInt with Reset

    A data type for booleans, defined as a single bit indicating true or false.

12.  trait BoolFactory extends AnyRef
13.  abstract class Bundle extends Record

    Base class for data types defined as a bundle of other data types.

    Base class for data types defined as a bundle of other data types.

    Usage: extend this class (either as an anonymous or named class) and define members variables of Data subtypes to be elements in the Bundle.

    Example of an anonymous IO bundle

    class MyModule extends Module {
      val io = IO(new Bundle {
        val in = Input(UInt(64.W))
        val out = Output(SInt(128.W))
      })
    }

    Or as a named class

    class Packet extends Bundle {
      val header = UInt(16.W)
      val addr   = UInt(16.W)
      val data   = UInt(32.W)
    }
    class MyModule extends Module {
      val inPacket = IO(Input(new Packet))
      val outPacket = IO(Output(new Packet))
      val reg = Reg(new Packet)
      reg := inPacket
      outPacket := reg
    }

    The fields of a Bundle are stored in an ordered Map called "elements" in reverse order of definition

    class MyBundle extends Bundle {
      val foo = UInt(8.W)
      val bar = UInt(8.W)
    }
    val wire = Wire(new MyBundle)
    wire.elements // VectorMap("bar" -> wire.bar, "foo" -> wire.foo)

14.  case class Character(bits: Bits) extends FirrtlFormat with Product with Serializable

    Format bits as Character

15.  abstract class ChiselEnum extends AnyRef
16.  class ChiselException extends Exception
17.  sealed class Clock extends Element
18.  type Connectable[T <: Data] = chisel3.connectable.Connectable[T]
19.  abstract class Data extends HasId with NamedComponent with SourceInfoDoc

    This forms the root of the type system for wire data types.

    This forms the root of the type system for wire data types. The data value must be representable as some number (need not be known at Chisel compile time) of bits, and must have methods to pack / unpack structured data to / from bits.

20.  case class Decimal(bits: Bits) extends FirrtlFormat with Product with Serializable

    Format bits as Decimal

21.  class Disable extends AnyRef

    API for handling disabling of simulation constructs

    API for handling disabling of simulation constructs

    Disables may be non-synthesizable so they can only be used for disabling simulation constructs

    The default disable is the "hasBeenReset" of the currently in scope reset. It can be set by the user via the withDisable API

    Users can access the current Disable with Module.disable

22.  abstract class Element extends Data

    Element is a leaf data type: it cannot contain other Data objects.

    Element is a leaf data type: it cannot contain other Data objects. Example uses are for representing primitive data types, like integers and bits.

23.  abstract class EnumType extends Element
24.  case class ExpectedAnnotatableException(message: String) extends BindingException with Product with Serializable

    A function expected annotatable hardware

25.  case class ExpectedChiselTypeException(message: String) extends BindingException with Product with Serializable

    A function expected a Chisel type but got a hardware object

26.  case class ExpectedHardwareException(message: String) extends BindingException with Product with Serializable

    A function expected a hardware object but got a Chisel type

27.  sealed abstract class FirrtlFormat extends Printable

    Superclass for Firrtl format specifiers for Bits

28.  sealed trait FixedIOBaseModule[A <: Data] extends BaseModule

    A module or external module whose IO is generated from a specific generator.

    A module or external module whose IO is generated from a specific generator. This module may have no additional IO created other than what is specified by its ioGenerator abstract member.

29.  class FixedIOExtModule[A <: Data] extends ExtModule with FixedIOBaseModule[A]

    A Chisel blackbox whose IO is determined by an IO generator.

    A Chisel blackbox whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

30.  class FixedIORawModule[A <: Data] extends RawModule with FixedIOBaseModule[A]

    A Chisel module whose IO is determined by an IO generator.

    A Chisel module whose IO is determined by an IO generator. This module cannot have additional IO created by modules that extend it.

31.  case class FullName(data: Data) extends Printable with Product with Serializable

    Put full name within parent namespace (eg.

    Put full name within parent namespace (eg. bundleName.field)

32.  sealed trait HasTarget extends AnyRef

    Exposes target information and suggestName functionality of a NamedComponent.

33.  case class Hexadecimal(bits: Bits) extends FirrtlFormat with Product with Serializable

    Format bits as Hexidecimal

34.  trait IgnoreSeqInBundle extends AnyRef

    Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.

    Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.

    Used to avoid raising an error/exception when a Seq is a public member of the bundle. This is useful if we those public Seq fields in the Bundle are unrelated to hardware construction.

35.  trait ImplicitClock extends AnyRef

    Provides an implicit Clock for use _within_ the RawModule

    Provides an implicit Clock for use _within_ the RawModule

    Be careful to define the Clock value before trying to use it. Due to Scala initialization order, the actual val defining the Clock must occur before any uses of the implicit Clock.

    Example:

    1. class MyModule extends RawModule with ImplicitClock {
         // Define a Clock value, it need not be called "implicitClock"
         val clk = IO(Input(Clock()))
         // Implement the virtual method to tell Chisel about this Clock value
         // Note that though this is a def, the actual Clock is assigned to a val (clk above)
         override protected def implicitClock = clk
         // Now we have a Clock to use in this RawModule
         val reg = Reg(UInt(8.W))
       }

36.  trait ImplicitReset extends AnyRef

    Provides an implicit Reset for use _within_ the RawModule

    Provides an implicit Reset for use _within_ the RawModule

    Be careful to define the Reset value before trying to use it. Due to Scala initialization order, the actual val defining the Reset object must occur before any uses of the implicit Reset.

    Example:

    1. class MyModule extends RawModule with ImplicitReset {
         // Define a Reset value, it need not be called "implicitReset"
         val rst = IO(Input(AsyncReset()))
         // Implement the virtual method to tell Chisel about this Reset value
         // Note that though this is a def, the actual Reset is assigned to a val (rst above)
         override protected def implicitReset = clk
         // Now we have a Reset to use in this RawModule
         // Registers also require a clock
         val clock = IO(Input(Clock()))
         val reg = withClock(clock)(RegInit(0.U)) // Combine with ImplicitClock to get rid of this withClock
       }

37.  trait InstanceId extends AnyRef

    Public API to access Node/Signal names.

    Public API to access Node/Signal names. currently, the node's name, the full path name, and references to its parent Module and component. These are only valid once the design has been elaborated, and should not be used during its construction.

38.  class InternalErrorException extends ChiselException
39.  sealed case class KnownWidth(value: Int) extends Width with Product with Serializable
40.  sealed class Mem[T <: Data] extends MemBase[T]

    A combinational/asynchronous-read, sequential/synchronous-write memory.

    A combinational/asynchronous-read, sequential/synchronous-write memory.

    Writes take effect on the rising clock edge after the request. Reads are combinational (requests will return data on the same cycle). Read-after-write hazards are not an issue.

    Note

    when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)

41.  sealed abstract class MemBase[T <: Data] extends HasId with NamedComponent with SourceInfoDoc
42.  case class MixedDirectionAggregateException(message: String) extends BindingException with Product with Serializable

    An aggregate had a mix of specified and unspecified directionality children

43.  abstract class Module extends RawModule with ImplicitClock with ImplicitReset

    Abstract base class for Modules, which behave much like Verilog modules.

    Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.

    Note

    Module instantiations must be wrapped in a Module() call.

44.  abstract class ModuleAspect extends RawModule with PseudoModule

    Used by Chisel Aspects to inject Chisel code into modules, after they have been elaborated.

    Used by Chisel Aspects to inject Chisel code into modules, after they have been elaborated. This is an internal API - don't use!

    It adds itself as an aspect to the module, which allows proper checking of connection and binding legality.

45.  case class MonoConnectException(message: String) extends ChiselException with Product with Serializable
46.  case class Name(data: Data) extends Printable with Product with Serializable

    Put innermost name (eg.

    Put innermost name (eg. field of bundle)

47.  trait Num[T <: Data] extends AnyRef

    Abstract trait defining operations available on numeric-like hardware data types.

    Abstract trait defining operations available on numeric-like hardware data types.

    T

    the underlying type of the number

48.  trait NumObject extends AnyRef

    NumbObject has a lot of convenience methods for converting between BigInts and Double and BigDecimal

49.  case class PString(str: String) extends Printable with Product with Serializable

    Wrapper for printing Scala Strings

50.  sealed abstract class Printable extends AnyRef

    Superclass of things that can be printed in the resulting circuit

    Superclass of things that can be printed in the resulting circuit

    Usually created using the custom string interpolator p"...". Printable string interpolation is similar to String interpolation in Scala For example:

    printf(p"The value of wire = $wire\n")

    This is equivalent to writing:

    printf("The value of wire = %d\n", wire)

    All Chisel data types have a method .toPrintable that gives a default pretty print that can be accessed via p"...". This works even for aggregate types, for example:

    val myVec = VecInit(5.U, 10.U, 13.U)
    printf(p"myVec = $myVec\n")
    // myVec = Vec(5, 10, 13)
    
    val myBundle = Wire(new Bundle {
      val foo = UInt()
      val bar = UInt()
    })
    myBundle.foo := 3.U
    myBundle.bar := 11.U
    printf(p"myBundle = $myBundle\n")
    // myBundle = Bundle(a -> 3, b -> 11)

    Users can override the default behavior of .toPrintable in custom Bundle and Record types.

51.  implicit final class PrintableHelper extends AnyVal

    Implicit for custom Printable string interpolator

52.  case class Printables(pables: Iterable[Printable]) extends Printable with Product with Serializable
53.  abstract class RawModule extends BaseModule

    Abstract base class for Modules that contain Chisel RTL.

    Abstract base class for Modules that contain Chisel RTL. This abstract base class is a user-defined module which does not include implicit clock and reset and supports multiple IO() declarations.

54.  case class RebindingException(message: String) extends BindingException with Product with Serializable

    Attempted to re-bind an already bound (directionality or hardware) object

55.  abstract class Record extends Aggregate

    Base class for Aggregates based on key values pairs of String and Data

    Base class for Aggregates based on key values pairs of String and Data

    Record should only be extended by libraries and fairly sophisticated generators. RTL writers should use Bundle. See Record#elements for an example.

56.  trait RequireAsyncReset extends Module

    Enforce that the Module.reset be Asynchronous (AsyncReset)

57.  trait RequireSyncReset extends Module

    Enforce that the Module.reset be Synchronous (Bool)

58.  sealed trait Reset extends Element with ToBoolable
59.  final class ResetType extends Element with Reset

    "Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool

    "Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool

    Note

    This shares a common interface with AsyncReset and Bool but is not their actual super type due to Bool inheriting from abstract class UInt

60.  sealed class SInt extends Bits with Num[SInt]

    A data type for signed integers, represented as a binary bitvector.

    A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.

61.  trait SIntFactory extends AnyRef
62.  trait SourceInfoDoc extends AnyRef

    Provides ScalaDoc information for "hidden" do_* methods

    Provides ScalaDoc information for "hidden" do_* methods

    Mix this into classes/objects that have do_* methods to get access to the shared SourceInfoTransformMacro ScalaDoc group and the lengthy groupdesc below.

63.  sealed abstract class SpecifiedDirection extends AnyRef

    User-specified directions.

64.  sealed class SyncReadMem[T <: Data] extends MemBase[T]

    A sequential/synchronous-read, sequential/synchronous-write memory.

    A sequential/synchronous-read, sequential/synchronous-write memory.

    Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.

    Note

    when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)

65.  sealed class UInt extends Bits with Num[UInt]

    A data type for unsigned integers, represented as a binary bitvector.

    A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.

66.  trait UIntFactory extends AnyRef
67.  sealed case class UnknownWidth() extends Width with Product with Serializable
68.  sealed class Vec[T <: Data] extends Aggregate with VecLike[T]

    A vector (array) of Data elements.

    A vector (array) of Data elements. Provides hardware versions of various collection transformation functions found in software array implementations.

    Careful consideration should be given over the use of Vec vs Seq or some other Scala collection. In general Vec only needs to be used when there is a need to express the hardware collection in a Reg or IO Bundle or when access to elements of the array is indexed via a hardware signal.

    Example of indexing into a Vec using a hardware address and where the Vec is defined in an IO Bundle

    val io = IO(new Bundle {
      val in = Input(Vec(20, UInt(16.W)))
      val addr = Input(UInt(5.W))
      val out = Output(UInt(16.W))
    })
    io.out := io.in(io.addr)

    T

    type of elements

    Note

    • when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
    • Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier

69.  trait VecFactory extends SourceInfoDoc
70.  trait VecLike[T <: Data] extends IndexedSeq[T] with HasId with SourceInfoDoc

    A trait for Vecs containing common hardware generators for collection operations.

71.  trait VerifPrintMacrosDoc extends AnyRef

    Scaladoc information for internal verification statement macros that are used in objects assert, assume and cover.

72.  abstract class VerificationStatement extends NamedComponent

    Base class for all verification statements: Assert, Assume, Cover, Stop and Printf.

73.  final class WhenContext extends AnyRef

    A WhenContext may represent a when, and elsewhen, or an otherwise.

    A WhenContext may represent a when, and elsewhen, or an otherwise. Since FIRRTL does not have an "elsif" statement, alternatives must be mapped to nested if-else statements inside the alternatives of the preceeding condition. In order to emit proper FIRRTL, it is necessary to keep track of the depth of nesting of the FIRRTL whens. Due to the "thin frontend" nature of Chisel3, it is not possible to know if a when or elsewhen has a succeeding elsewhen or otherwise; therefore, this information is added by preprocessing the command queue.

74.  sealed abstract class Width extends AnyRef
75.  trait WireFactory extends AnyRef
76.  implicit class fromBigIntToLiteral extends AnyRef

    These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.

    These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.

    Also provides .asBool to scala.Boolean and .asUInt to String

    Note that, for stylistic reasons, one should avoid extracting immediately after this call using apply, ie. 0.asUInt(1)(0) due to potential for confusion (the 1 is a bit length and the 0 is a bit extraction position). Prefer storing the result and then extracting from it.

    Implementation note: the empty parameter list (like U()) is necessary to prevent interpreting calls that have a non-Width parameter as a chained apply, otherwise things like 0.asUInt(16) (instead of 16.W) compile without error and produce undesired results.

77.  implicit class fromBooleanToLiteral extends AnyRef
78.  implicit class fromIntToLiteral extends fromBigIntToLiteral
79.  implicit class fromIntToWidth extends AnyRef
80.  implicit class fromLongToLiteral extends fromBigIntToLiteral
81.  implicit class fromStringToLiteral extends AnyRef