Value Members

1.  val Connectable: chisel3.connectable.Connectable.type
2.  final val deprecatedMFCMessage: String("this feature will not be supported as part of the migration to the MLIR-based FIRRTL Compiler (MFC). For more information about this migration, please see the Chisel ROADMAP.md.")
3.  final val deprecatedPublicAPIMsg: String("APIs in chisel3.internal are not intended to be public")
4.  def getDataElements(a: Aggregate): Seq[Element]
5.  implicit def string2Printable(str: String): Printable
6.  object ActualDirection
7.  object AsyncReset
8.  object Bits extends UIntFactory
9.  object Bool extends BoolFactory
10.  case object BuildInfo extends Product with Serializable

    This object was generated by sbt-buildinfo.

11.  object Clock
12.  object Const

    Create a constant type in FIRRTL, which is guaranteed to take a single constant value.

13.  object Data
14.  object Disable
15.  case object DontCare extends Element with ConnectableDocs with Product with Serializable

    RHS (source) for Invalidate API.

    RHS (source) for Invalidate API. Causes connection logic to emit a DefInvalid when connected to an output port (or wire).

16.  object FirrtlFormat
17.  object FlatIO

    The same as IO except there is no prefix when given a Record or Bundle.

    The same as IO except there is no prefix when given a Record or Bundle. For Element (UInt, etc.) or Vec types, this is the same as IO. It is also the same as IO for chisel3.probe.Probe types.

    Example:

    1. class MyBundle extends Bundle {
         val foo = Input(UInt(8.W))
         val bar = Output(UInt(8.W))
       }
       class MyModule extends Module {
         val io = FlatIO(new MyBundle)
         // input  [7:0] foo,
         // output [7:0] bar
       }

18.  object Flipped
19.  object HasTarget
20.  object IO
21.  object Input

    Input, Output, and Flipped are used to define the directions of Module IOs.

    Input, Output, and Flipped are used to define the directions of Module IOs.

    Note that they currently clone their source argument, including its bindings.

    Thus, an error will be thrown if these are used on bound Data

22.  object Mem
23.  object Module extends SourceInfoDoc
24.  object Mux extends SourceInfoDoc
25.  object Num extends NumObject
26.  object Output
27.  case object Percent extends Printable with Product with Serializable

    Represents escaped percents

28.  object Printable
29.  object Reg

    Utility for constructing hardware registers

    Utility for constructing hardware registers

    The width of a Reg (inferred or not) is copied from the type template

    val r0 = Reg(UInt()) // width is inferred
    val r1 = Reg(UInt(8.W)) // width is set to 8
    
    val r2 = Reg(Vec(4, UInt())) // width is inferred
    val r3 = Reg(Vec(4, UInt(8.W))) // width of each element is set to 8
    
    class MyBundle {
      val unknown = UInt()
      val known   = UInt(8.W)
    }
    val r4 = Reg(new MyBundle)
    // Width of r4.unknown is inferred
    // Width of r4.known is set to 8

30.  object RegInit

    Utility for constructing hardware registers with an initialization value.

    Utility for constructing hardware registers with an initialization value.

    The register is set to the initialization value when the current implicit reset is high

    The two forms of RegInit differ in how the type and width of the resulting Reg are specified.

    Single Argument

    The single argument form uses the argument to specify both the type and reset value. For non-literal Bits, the width of the Reg will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:

    1. Literal Bits initializer: width will be set to match

    val r1 = RegInit(1.U) // width will be inferred to be 1
    val r2 = RegInit(1.U(8.W)) // width is set to 8

    2. Non-Literal Element initializer - width will be inferred

    val x = Wire(UInt())
    val y = Wire(UInt(8.W))
    val r1 = RegInit(x) // width will be inferred
    val r2 = RegInit(y) // width will be inferred

    3. Aggregate initializer - width will be set to match the aggregate

    class MyBundle extends Bundle {
      val unknown = UInt()
      val known   = UInt(8.W)
    }
    val w1 = Reg(new MyBundle)
    val w2 = RegInit(w1)
    // Width of w2.unknown is inferred
    // Width of w2.known is set to 8

    Double Argument

    The double argument form allows the type of the Reg and the default connection to be specified independently.

    The width inference semantics for RegInit with two arguments match those of Reg. The first argument to RegInit is the type template which defines the width of the Reg in exactly the same way as the only argument to Wire.

    More explicitly, you can reason about RegInit with multiple arguments as if it were defined as:

    def RegInit[T <: Data](t: T, init: T): T = {
      val x = Reg(t)
      x := init
      x
    }

31.  object RegNext

    Utility for constructing one-cycle delayed versions of signals

    Utility for constructing one-cycle delayed versions of signals

    The width of a RegNext is not set based on the next or init connections for Element types. In the following example, the width of bar will not be set and will be inferred by the FIRRTL compiler.

    val foo = Reg(UInt(4.W))         // width is 4
    val bar = RegNext(foo)           // width is unset

    If you desire an explicit width, do not use RegNext and instead use a register with a specified width:

    val foo = Reg(UInt(4.W))         // width is 4
    val bar = Reg(chiselTypeOf(foo)) // width is 4
    bar := foo

    Also note that a RegNext of a Bundle will have it's width set for Aggregate types.

    class MyBundle extends Bundle {
      val x = UInt(4.W)
    }
    val foo = Wire(new MyBundle)     // the width of foo.x is 4
    val bar = RegNext(foo)           // the width of bar.x is 4

32.  object Reset
33.  object SInt extends SIntFactory
34.  object SpecifiedDirection
35.  object SyncReadMem
36.  object UInt extends UIntFactory
37.  object Vec extends VecFactory
38.  object VecInit extends SourceInfoDoc
39.  object Width
40.  object Wire extends WireFactory

    Utility for constructing hardware wires

    Utility for constructing hardware wires

    The width of a Wire (inferred or not) is copied from the type template

    val w0 = Wire(UInt()) // width is inferred
    val w1 = Wire(UInt(8.W)) // width is set to 8
    
    val w2 = Wire(Vec(4, UInt())) // width is inferred
    val w3 = Wire(Vec(4, UInt(8.W))) // width of each element is set to 8
    
    class MyBundle {
      val unknown = UInt()
      val known   = UInt(8.W)
    }
    val w4 = Wire(new MyBundle)
    // Width of w4.unknown is inferred
    // Width of w4.known is set to 8

41.  object WireDefault extends WireDefaultImpl

    Utility for constructing hardware wires with a default connection

    Utility for constructing hardware wires with a default connection

    The two forms of WireDefault differ in how the type and width of the resulting Wire are specified.

    Single Argument

    The single argument form uses the argument to specify both the type and default connection. For non-literal Bits, the width of the Wire will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:

    1. Literal Bits initializer: width will be set to match

    val w1 = WireDefault(1.U) // width will be inferred to be 1
    val w2 = WireDefault(1.U(8.W)) // width is set to 8

    2. Non-Literal Element initializer - width will be inferred

    val x = Wire(UInt())
    val y = Wire(UInt(8.W))
    val w1 = WireDefault(x) // width will be inferred
    val w2 = WireDefault(y) // width will be inferred

    3. Aggregate initializer - width will be set to match the aggregate

    class MyBundle {
      val unknown = UInt()
      val known   = UInt(8.W)
    }
    val w1 = Wire(new MyBundle)
    val w2 = WireDefault(w1)
    // Width of w2.unknown is inferred
    // Width of w2.known is set to 8

    Double Argument

    The double argument form allows the type of the Wire and the default connection to be specified independently.

    The width inference semantics for WireDefault with two arguments match those of Wire. The first argument to WireDefault is the type template which defines the width of the Wire in exactly the same way as the only argument to Wire.

    More explicitly, you can reason about WireDefault with multiple arguments as if it were defined as:

    def WireDefault[T <: Data](t: T, init: T): T = {
      val x = Wire(t)
      x := init
      x
    }

42.  object WireInit extends WireDefaultImpl

    Utility for constructing hardware wires with a default connection

    Utility for constructing hardware wires with a default connection

    Alias for WireDefault.

    Note

    The Init in WireInit refers to a "default" connection. This is in contrast to RegInit where the Init refers to a value on reset.

43.  object assert extends VerifPrintMacrosDoc
44.  object assume extends VerifPrintMacrosDoc
45.  object chiselTypeOf

    Returns the chisel type of a hardware object, allowing other hardware to be constructed from it.

46.  object cover extends VerifPrintMacrosDoc
47.  object dontTouch

    Marks that a signal's leaves are an optimization barrier to Chisel and the FIRRTL compiler.

    Marks that a signal's leaves are an optimization barrier to Chisel and the FIRRTL compiler. This has the effect of guaranteeing that a signal will not be removed.

    Example:

    1. class MyModule extends Module {
         val io = IO(new Bundle {
           val a = Input(UInt(32.W))
           val b = Output(UInt(32.W))
         })
         io.b := io.a
         val dead = io.a +% 1.U // normally dead would be pruned by DCE
         dontTouch(dead) // Marking it as such will preserve it
       }

    Note

    Because this is an optimization barrier, constants will not be propagated through a signal's leaves marked as dontTouch.

48.  object emitVerilog
49.  object getVerilogString
50.  object layer

    This object contains Chisel language features for creating layers.

    This object contains Chisel language features for creating layers. Layers are collections of hardware that are not always present in the circuit. Layers are intended to be used to hold verification or debug code.

51.  object printf

    Prints a message in simulation

    Prints a message in simulation

    See apply methods for use

52.  object stop
53.  object suppressEnumCastWarning

    Suppress enum cast warnings

    Suppress enum cast warnings

    Users should use <EnumType>.safe when possible.

    This is primarily used for casting from UInt to a Bundle type that contains an Enum.

    class MyBundle extends Bundle {
      val addr = UInt(8.W)
      val op = OpEnum()
    }
    
    // Since this is a cast to a Bundle, cannot use OpCode.safe
    val bundle = suppressEnumCastWarning {
      someUInt.asTypeOf(new MyBundle)
    }

54.  object when
55.  object withClock
56.  object withClockAndReset
57.  object withDisable

    Creates a new Disable scope

58.  object withReset
59.  object withoutIO