Packages

object Reg

Utility for constructing hardware registers

The width of a Reg (inferred or not) is copied from the type template

val r0 = Reg(UInt()) // width is inferred
val r1 = Reg(UInt(8.W)) // width is set to 8

val r2 = Reg(Vec(4, UInt())) // width is inferred
val r3 = Reg(Vec(4, UInt(8.W))) // width of each element is set to 8

class MyBundle {
  val unknown = UInt()
  val known   = UInt(8.W)
}
val r4 = Reg(new MyBundle)
// Width of r4.unknown is inferred
// Width of r4.known is set to 8
Source
Reg.scala
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  1. final def !=(arg0: Any): Boolean
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  2. final def ##: Int
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  3. final def ==(arg0: Any): Boolean
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  4. def apply[T <: Data](source: => T)(implicit sourceInfo: SourceInfo): T

    Construct a Reg from a type template with no initialization value (reset is ignored).

    Construct a Reg from a type template with no initialization value (reset is ignored). Value will not change unless the Reg is given a connection.

  5. final def asInstanceOf[T0]: T0
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  6. def clone(): AnyRef
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  7. final def eq(arg0: AnyRef): Boolean
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  9. def finalize(): Unit
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  10. final def getClass(): Class[_ <: AnyRef]
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  11. def hashCode(): Int
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  12. final def isInstanceOf[T0]: Boolean
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  13. final def ne(arg0: AnyRef): Boolean
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  14. final def notify(): Unit
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  15. final def notifyAll(): Unit
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  16. final def synchronized[T0](arg0: => T0): T0
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  17. def toString(): String
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  18. final def wait(): Unit
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  19. final def wait(arg0: Long, arg1: Int): Unit
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  20. final def wait(arg0: Long): Unit
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