The "mono-direction connection operator", aka the "coercion operator".

For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '#' means to ignore flips, always drive from producer to consumer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

The "mono-direction connection operator", aka the "coercion operator".

For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '#' means to ignore flips, always drive from producer to consumer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

The "mono-direction connection operator", aka the "coercion operator".

For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '#' means to ignore flips, always drive from producer to consumer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

The "aligned connection operator" between a producer and consumer.

For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '<' means to connect from producer to consumer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes:

• Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected

The "aligned connection operator" between a producer and consumer.

For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '<' means to connect from producer to consumer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes:

• Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected

The "aligned connection operator" between a producer and consumer.

For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '<' means to connect from producer to consumer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes:

• Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected

The "bi-direction connection operator", aka the "tur-duck-en operator"

For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '<' means to connect from producer to consumer
• '>' means to connect from consumer to producer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

Additional notes:

• Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
• If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
• "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>

The "bi-direction connection operator", aka the "tur-duck-en operator"

For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '<' means to connect from producer to consumer
• '>' means to connect from consumer to producer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

Additional notes:

• Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
• If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
• "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>

The "bi-direction connection operator", aka the "tur-duck-en operator"

For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '<' means to connect from producer to consumer
• '>' means to connect from consumer to producer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

Additional notes:

• Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
• If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
• "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>

The "strong connect" operator.

For chisel3._, this operator is mono-directioned; all sub-elements of this will be driven by sub-elements of that.

• Equivalent to this :#= that

For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=

• Equivalent to this :<>= that

The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '>' means to connect from consumer to producer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes:

• Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected

The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '>' means to connect from consumer to producer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes:

• Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected

The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

Symbol reference:

• ':' is the consumer side
• '=' is the producer side
• '>' means to connect from consumer to producer

The following restrictions apply:

• The Chisel type of consumer and producer must be the "same shape" recursively:
  • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
  • All vector types are the same length
  • All bundle types have the same member names, but the flips of members can be different between producer and consumer
• The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

Additional notes:

• Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected

The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

For chisel3._, uses the chisel3.internal.BiConnect algorithm; sub-elements of that may end up driving sub-elements of this

• Complicated semantics, hard to write quickly, will likely be deprecated in the future

For Chisel._, emits the FIRRTL.<- operator

• Equivalent to this :<>= that without the restrictions that bundle field names and vector sizes must match

Dynamic recursive equality operator for generic Data

Implementation of cloneType that is [optionally for Record] overridden by the compiler plugin

The list of parameter accessors used in the constructor of this chisel3.Record.

Get result of each field in decoding result

Static cast to a super type

Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.

x.asTypeOf(that) performs the inverse operation of x := that.toBits.

Reinterpret cast to UInt.

Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).

If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.

Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.

Name for Pretty Printing

Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

cloneType must be defined for any Chisel object extending Data. It is responsible for constructing a basic copy of the object being cloned.

Select members of base to exclude

Adds base to excludes

Select members of base to exclude and static cast to a new type

Programmatically select members of base to exclude and static cast to a new type

Exclude probes

Returns a Seq of the immediate contents of this Aggregate, in order.

Returns the width, in bits, if currently known.

Returns whether the width is currently known.

Return an Aggregate's literal value if it is a literal, None otherwise. If any element of the aggregate is not a literal (or DontCare), the result isn't a literal.

Return an Aggregate's literal value if it is a literal, otherwise an exception is thrown. If any element of the aggregate is not a literal with a defined width, the result isn't a literal.

True if no members are waived or squeezed or excluded

Returns a read-only view of this Data

It is illegal to connect to the return value of this method. This Data this method is called on must be a hardware type.

Select members of base to squeeze

Adds base to squeezes

Squeeze all members of base

Squeeze all members of base and upcast to super type

Programmatically select members of base to squeeze

Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

Returns a FIRRTL ComponentName that references this object

Default "pretty-print" implementation Analogous to printing a Map Results in "$className(elt0.name -> elt0.value, ...)"

Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

If root is defined, the target is a hierarchical path starting from root.

If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

The collection of chisel3.Data

This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to Vec). For example:

// Assume we have some type MyRecord that creates a Record from the ListMap
val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W)))
// "buzz" is higher order because it was added later than "fizz"
record("fizz") := "hdead".U
record("buzz") := "hbeef".U
val uint = record.asUInt
assert(uint === "hbeefdead".U) // This will pass

Returns a FIRRTL ReferenceTarget that references this object

A non-ambiguous name of this Data for use in generated Verilog names

Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members

Select members of base to waive

Waive all members of base

Waive all members of base and static cast to a new type

Select members of base to waive and static cast to a new type

Programmatically select members of base to waive and static cast to a new type

Returns Some(width) if the width is known, else None.