class FibonacciLFSR extends PRNG with LFSR
Fibonacci Linear Feedback Shift Register (LFSR) generator.
A Fibonacci LFSR can be generated by defining a width and a set of tap points (corresponding to a polynomial). An optional initial seed and a reduction operation (XOR, the default, or XNOR) can be used to augment the generated hardware. The resulting hardware has support for a run-time programmable seed (via PRNGIO.seed) and conditional increment (via PRNGIO.increment).
If the user specifies a seed, then a compile-time check is added that they are not initializing the LFSR to a state which will cause it to lock up. If the user does not set a seed, then the least significant bit of the state will be set or reset based on the choice of reduction operator.
In the example below, a 4-bit Fibonacci LFSR is constructed. Tap points are defined as four and three (using LFSR convention of indexing from one). This results in the hardware configuration shown in the diagram.
val lfsr4 = Module(new FibonacciLFSR(4, Set(4, 3)) // +---+ // +-------------->|XOR|-------------------------------------------------------+ // | +---+ | // | +-------+ ^ +-------+ +-------+ +-------+ | // | | | | | | | | | | | // +---+ x^4 |<----+-----| x^3 |<----------| x^2 |<----------| x^1 |<--+ // | | | | | | | | // +-------+ +-------+ +-------+ +-------+
If you require a maximal period Fibonacci LFSR of a specific width, you can use MaxPeriodFibonacciLFSR. If you only require a pseudorandom UInt you can use the FibonacciLFSR companion object.
- Source
- FibonacciLFSR.scala
- See also
https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Fibonacci_LFSRs
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- by BaseModuleExtensions
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- by any2stringadd
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- by Ensuring
- by ArrowAssoc
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- Public
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Instance Constructors
- new FibonacciLFSR(width: Int, taps: Set[Int], seed: Option[BigInt] = Some(1), reduction: LFSRReduce = XOR, step: Int = 1, updateSeed: Boolean = false)
- width
the width of the LFSR
- taps
a set of tap points to use when constructing the LFSR
- seed
an initial value for internal LFSR state. If None, then the LFSR state LSB will be set to a known safe value on reset (to prevent lock up).
- reduction
- step
the number of state updates per cycle
- updateSeed
if true, when loading the seed the state will be updated as if the seed were the current state, if false, the state will be set to the seed
Value Members
- final val clock: Clock
- Definition Classes
- Module
- final val definitionIdentifier: String
Represents an eagerly-determined unique and descriptive identifier for this module
Represents an eagerly-determined unique and descriptive identifier for this module
- Definition Classes
- BaseModule
- def delta(s: Seq[Bool]): Seq[Bool]
State update function
- def desiredName: String
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The name of a module approximates the behavior of the Java Reflection
getSimpleName
method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:- Anonymous modules will get an
"_Anon"
tag - Modules defined in functions will use their class name and not a numeric name- Definition Classes
- BaseModule
- Note
If you want a custom or parametric name, override this method.
- def endIOCreation()(implicit si: SourceInfo): Unit
Disallow any more IO creation for this module.
Disallow any more IO creation for this module.
- Definition Classes
- BaseModule
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- def hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
Signal name (for simulation).
Signal name (for simulation).
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: PRNGIO
- Definition Classes
- PRNG
- def localModulePrefix: Option[String]
Additional module prefix, applies to this module if defined (unless localModulePrefixAppliesToSelf is false) and all children.
Additional module prefix, applies to this module if defined (unless localModulePrefixAppliesToSelf is false) and all children.
- Definition Classes
- BaseModule
- def localModulePrefixAppliesToSelf: Boolean
Should localModulePrefix apply to this module? Defaults to true.
Should localModulePrefix apply to this module? Defaults to true.
Users should override to false if localModulePrefix should apply only to children.
- Definition Classes
- BaseModule
- def localModulePrefixUseSeparator: Boolean
Should the localModulePrefix include a separator between prefix and the Module name
Should the localModulePrefix include a separator between prefix and the Module name
Defaults to true, users can override to false if they don't want a separator.
- Definition Classes
- BaseModule
- final val modulePrefix: String
The resolved module prefix used for this Module.
The resolved module prefix used for this Module.
Includes localModulePrefix if defined and if localModulePrefixAppliesToSelf is true.
- Definition Classes
- BaseModule
- final lazy val name: String
Legalized name of this module.
Legalized name of this module.
- Definition Classes
- BaseModule
- final def nextState(s: Seq[Bool]): Seq[Bool]
The method that will be used to update the state of this PRNG
The method that will be used to update the state of this PRNG
- s
input state
- returns
the next state after
step
applications of PRNG.delta
- Definition Classes
- PRNG
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val reduction: LFSRReduce
The binary reduction operation used by this LFSR, either XOR or XNOR.
The binary reduction operation used by this LFSR, either XOR or XNOR. This has the effect of mandating what seed is invalid.
- Definition Classes
- FibonacciLFSR → LFSR
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
Override this to explicitly set the type of reset you want on this module , before any reset inference
Override this to explicitly set the type of reset you want on this module , before any reset inference
- Definition Classes
- Module
- val seed: Option[BigInt]
- Definition Classes
- PRNG
- def suggestName(seed: => String): FibonacciLFSR.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than
autoSeed
, in that regardless of whetherautoSeed
was called, suggestName will always take precedence.- seed
The seed for the name of this component
- returns
this object
- Definition Classes
- HasId
- final def toAbsoluteTarget: IsModule
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- def toDefinition: Definition[FibonacciLFSR]
- Implicit
- This member is added by an implicit conversion from FibonacciLFSR toBaseModuleExtensions[FibonacciLFSR] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
- Definition Classes
- BaseModuleExtensions
- final def toNamed: ModuleName
Returns a FIRRTL ModuleName that references this object
Returns a FIRRTL ModuleName that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- final def toRelativeTarget(root: Option[BaseModule]): IsModule
Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.
Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.
If
root
is defined, the target is a hierarchical path starting fromroot
.If
root
is not defined, the target is a hierarchical path equivalent totoAbsoluteTarget
.- Definition Classes
- BaseModule
- Note
If
,root
is defined, and has not finished elaboration, this must be called withinatModuleBodyEnd
.The BaseModule must be a descendant of
,root
, if it is defined.This doesn't have special handling for Views.
- final def toRelativeTargetToHierarchy(root: Option[Hierarchy[BaseModule]]): IsModule
Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.
Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.
If
root
is defined, the target is a hierarchical path starting fromroot
.If
root
is not defined, the target is a hierarchical path equivalent totoAbsoluteTarget
.- Definition Classes
- BaseModule
- Note
If
,root
is defined, and has not finished elaboration, this must be called withinatModuleBodyEnd
.The BaseModule must be a descendant of
,root
, if it is defined.This doesn't have special handling for Views.
- final def toTarget: ModuleTarget
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- val width: Int
- Definition Classes
- PRNG
Shadowed Implicit Value Members
- def toInstance: Instance[FibonacciLFSR]
- Implicit
- This member is added by an implicit conversion from FibonacciLFSR toBaseModuleExtensions[FibonacciLFSR] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
- Shadowing
- This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
To access this member you can use a type ascription:(fibonacciLFSR: BaseModuleExtensions[FibonacciLFSR]).toInstance
- Definition Classes
- BaseModuleExtensions
Deprecated Value Members
- def toInstance: Instance[FibonacciLFSR]
- Implicit
- This member is added by an implicit conversion from FibonacciLFSR toIsInstantiableExtensions[FibonacciLFSR] performed by method IsInstantiableExtensions in chisel3.experimental.hierarchy.core.IsInstantiable.
- Shadowing
- This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
To access this member you can use a type ascription:(fibonacciLFSR: IsInstantiableExtensions[FibonacciLFSR]).toInstance
- Definition Classes
- IsInstantiableExtensions
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 7.0.0) Use of @instantiable on user-defined types is deprecated. Implement Lookupable for your type instead.
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.