Packages

  • package root

    This is the documentation for Chisel.

    This is the documentation for Chisel.

    Package structure

    The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

    The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

    Utility objects and methods are found in the util package.

    The testers package defines the basic interface for chisel testers.

    Definition Classes
    root
  • package chisel3

    This package contains the main chisel3 API.

    This package contains the main chisel3 API.

    Definition Classes
    root
  • package util

    The util package provides extensions to core chisel for common hardware components and utility functions

    The util package provides extensions to core chisel for common hardware components and utility functions

    Definition Classes
    chisel3
  • package random
    Definition Classes
    util
  • FibonacciLFSR
  • GaloisLFSR
  • LFSR
  • LFSRReduce
  • MaxPeriodFibonacciLFSR
  • MaxPeriodGaloisLFSR
  • PRNG
  • PRNGIO
  • XNOR
  • XOR

class FibonacciLFSR extends PRNG with LFSR

Fibonacci Linear Feedback Shift Register (LFSR) generator.

A Fibonacci LFSR can be generated by defining a width and a set of tap points (corresponding to a polynomial). An optional initial seed and a reduction operation (XOR, the default, or XNOR) can be used to augment the generated hardware. The resulting hardware has support for a run-time programmable seed (via PRNGIO.seed) and conditional increment (via PRNGIO.increment).

If the user specifies a seed, then a compile-time check is added that they are not initializing the LFSR to a state which will cause it to lock up. If the user does not set a seed, then the least significant bit of the state will be set or reset based on the choice of reduction operator.

In the example below, a 4-bit Fibonacci LFSR is constructed. Tap points are defined as four and three (using LFSR convention of indexing from one). This results in the hardware configuration shown in the diagram.

val lfsr4 = Module(new FibonacciLFSR(4, Set(4, 3))
//                 +---+
// +-------------->|XOR|-------------------------------------------------------+
// |               +---+                                                       |
// |   +-------+     ^     +-------+           +-------+           +-------+   |
// |   |       |     |     |       |           |       |           |       |   |
// +---+  x^4  |<----+-----|  x^3  |<----------|  x^2  |<----------|  x^1  |<--+
//     |       |           |       |           |       |           |       |
//     +-------+           +-------+           +-------+           +-------+

If you require a maximal period Fibonacci LFSR of a specific width, you can use MaxPeriodFibonacciLFSR. If you only require a pseudorandom UInt you can use the FibonacciLFSR companion object.

Source
FibonacciLFSR.scala
See also

https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Fibonacci_LFSRs

Known Subclasses
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Inherited
  1. FibonacciLFSR
  2. LFSR
  3. PRNG
  4. Module
  5. ImplicitReset
  6. ImplicitClock
  7. RawModule
  8. BaseModule
  9. IsInstantiable
  10. HasId
  11. InstanceId
  12. AnyRef
  13. Any
Implicitly
  1. by BaseModuleExtensions
  2. by IsInstantiableExtensions
  3. by any2stringadd
  4. by StringFormat
  5. by Ensuring
  6. by ArrowAssoc
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new FibonacciLFSR(width: Int, taps: Set[Int], seed: Option[BigInt] = Some(1), reduction: LFSRReduce = XOR, step: Int = 1, updateSeed: Boolean = false)

    width

    the width of the LFSR

    taps

    a set of tap points to use when constructing the LFSR

    seed

    an initial value for internal LFSR state. If None, then the LFSR state LSB will be set to a known safe value on reset (to prevent lock up).

    reduction

    the reduction operation (either XOR or XNOR)

    step

    the number of state updates per cycle

    updateSeed

    if true, when loading the seed the state will be updated as if the seed were the current state, if false, the state will be set to the seed

Value Members

  1. final val clock: Clock
    Definition Classes
    Module
  2. final val definitionIdentifier: String

    Represents an eagerly-determined unique and descriptive identifier for this module

    Represents an eagerly-determined unique and descriptive identifier for this module

    Definition Classes
    BaseModule
  3. def delta(s: Seq[Bool]): Seq[Bool]

    State update function

    State update function

    s

    input state

    returns

    the next state

    Definition Classes
    FibonacciLFSRPRNG
  4. def desiredName: String

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The name of a module approximates the behavior of the Java Reflection getSimpleName method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:

    - Anonymous modules will get an "_Anon" tag - Modules defined in functions will use their class name and not a numeric name

    Definition Classes
    BaseModule
    Note

    If you want a custom or parametric name, override this method.

  5. def endIOCreation()(implicit si: SourceInfo): Unit

    Disallow any more IO creation for this module.

    Disallow any more IO creation for this module.

    Definition Classes
    BaseModule
  6. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  7. def hasSeed: Boolean

    returns

    Whether either autoName or suggestName has been called

    Definition Classes
    HasId
  8. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  9. def instanceName: String

    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  10. val io: PRNGIO
    Definition Classes
    PRNG
  11. def localModulePrefix: Option[String]

    Additional module prefix, applies to this module if defined (unless localModulePrefixAppliesToSelf is false) and all children.

    Additional module prefix, applies to this module if defined (unless localModulePrefixAppliesToSelf is false) and all children.

    Definition Classes
    BaseModule
  12. def localModulePrefixAppliesToSelf: Boolean

    Should localModulePrefix apply to this module? Defaults to true.

    Should localModulePrefix apply to this module? Defaults to true.

    Users should override to false if localModulePrefix should apply only to children.

    Definition Classes
    BaseModule
  13. def localModulePrefixUseSeparator: Boolean

    Should the localModulePrefix include a separator between prefix and the Module name

    Should the localModulePrefix include a separator between prefix and the Module name

    Defaults to true, users can override to false if they don't want a separator.

    Definition Classes
    BaseModule
  14. final val modulePrefix: String

    The resolved module prefix used for this Module.

    The resolved module prefix used for this Module.

    Includes localModulePrefix if defined and if localModulePrefixAppliesToSelf is true.

    Definition Classes
    BaseModule
  15. final lazy val name: String

    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  16. final def nextState(s: Seq[Bool]): Seq[Bool]

    The method that will be used to update the state of this PRNG

    The method that will be used to update the state of this PRNG

    s

    input state

    returns

    the next state after step applications of PRNG.delta

    Definition Classes
    PRNG
  17. def parentModName: String
    Definition Classes
    HasId → InstanceId
  18. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  19. def pathName: String
    Definition Classes
    HasId → InstanceId
  20. val reduction: LFSRReduce

    The binary reduction operation used by this LFSR, either XOR or XNOR.

    The binary reduction operation used by this LFSR, either XOR or XNOR. This has the effect of mandating what seed is invalid.

    Definition Classes
    FibonacciLFSRLFSR
  21. final val reset: Reset
    Definition Classes
    Module
  22. def resetType: Type

    Override this to explicitly set the type of reset you want on this module , before any reset inference

    Override this to explicitly set the type of reset you want on this module , before any reset inference

    Definition Classes
    Module
  23. val seed: Option[BigInt]
    Definition Classes
    PRNG
  24. def suggestName(seed: => String): FibonacciLFSR.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

    seed

    The seed for the name of this component

    returns

    this object

    Definition Classes
    HasId
  25. final def toAbsoluteTarget: IsModule

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  26. def toDefinition: Definition[FibonacciLFSR]
    Implicit
    This member is added by an implicit conversion from FibonacciLFSR toBaseModuleExtensions[FibonacciLFSR] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
    Definition Classes
    BaseModuleExtensions
  27. final def toNamed: ModuleName

    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  28. final def toRelativeTarget(root: Option[BaseModule]): IsModule

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    BaseModule
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The BaseModule must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  29. final def toRelativeTargetToHierarchy(root: Option[Hierarchy[BaseModule]]): IsModule

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    BaseModule
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The BaseModule must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  30. final def toTarget: ModuleTarget

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  31. val width: Int
    Definition Classes
    PRNG

Shadowed Implicit Value Members

  1. def toInstance: Instance[FibonacciLFSR]
    Implicit
    This member is added by an implicit conversion from FibonacciLFSR toBaseModuleExtensions[FibonacciLFSR] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
    Shadowing
    This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
    To access this member you can use a type ascription:
    (fibonacciLFSR: BaseModuleExtensions[FibonacciLFSR]).toInstance
    Definition Classes
    BaseModuleExtensions

Deprecated Value Members

  1. def toInstance: Instance[FibonacciLFSR]
    Implicit
    This member is added by an implicit conversion from FibonacciLFSR toIsInstantiableExtensions[FibonacciLFSR] performed by method IsInstantiableExtensions in chisel3.experimental.hierarchy.core.IsInstantiable.
    Shadowing
    This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
    To access this member you can use a type ascription:
    (fibonacciLFSR: IsInstantiableExtensions[FibonacciLFSR]).toInstance
    Definition Classes
    IsInstantiableExtensions
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 7.0.0) Use of @instantiable on user-defined types is deprecated. Implement Lookupable for your type instead.