Type Members

1.  trait AffectsChiselPrefix extends AnyRef

   Generate prefixes from values of this type in the Chisel compiler plugin

   Generate prefixes from values of this type in the Chisel compiler plugin

   Users can mixin this trait to tell the Chisel compiler plugin to include the names of vals of this type when generating prefixes for naming Data and Mem instances. This is generally useful whenever creating a class that contains Data, Mem, or Module instances but does not itself extend Data or Module.

   Example:

   1. import chisel3._
      import chisel3.experimental.AffectsChiselPrefix
      
      class MyModule extends Module {
        // Note: This contains a Data but is not a named component itself
        class NotAData extends AffectsChiselPrefix {
          val value = Wire(Bool())
        }
      
        // Name with AffectsChiselPrefix:    "nonData_value"
        // Name without AffectsChiselPrefix: "value"
        val nonData = new NotAData
      
        // Name with AffectsChiselPrefix:    "nonData2_value"
        // Name without AffectsChiselPrefix: "value_1"
        val nonData2 = new NotAData
      }

   See also

   See the compiler plugin documentation for more information on this process.

2.  final class Analog extends Element

   Data type for representing bidirectional bitvectors of a given width

   Data type for representing bidirectional bitvectors of a given width

   Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout) pins. There is currently no support for reading or writing of Analog types within Chisel code.

   Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no effect.

   Analog types are generally connected using the bidirectional attach mechanism, but also support limited bulkconnect <>. Analog types are only allowed to be bulk connected *once* in a given module. This is to prevent any surprising consequences of last connect semantics.

   Note

   This API is experimental and subject to change

3.  abstract class BaseModule extends HasId with IsInstantiable

   Abstract base class for Modules, an instantiable organizational unit for RTL.

4.  class BundleLiteralException extends ChiselException
5.  trait ChiselAnnotation extends AnyRef

   Interface for Annotations in Chisel

   Interface for Annotations in Chisel

   Defines a conversion to a corresponding FIRRTL Annotation

6.  trait ChiselMultiAnnotation extends AnyRef

   Enhanced interface for Annotations in Chisel

   Enhanced interface for Annotations in Chisel

   Defines a conversion to corresponding FIRRTL Annotation(s)

7.  sealed trait ChiselSubtypeOf[A, B] extends AnyRef

   Enforces that A is a Chisel subtype of B.

   Enforces that A is a Chisel subtype of B.

   A is a Chisel subtype of B if A contains all of B's fields (same names and same types). Only public fields that are subtypes of chisel3.Data are considered when checking for containment.

   In the following example A is a Chisel subtype of B:

   class A extends Bundle {
     val x = UInt(3.W)
     val y = UInt(3.W)
     val z = UInt(3.W)
   }
   class B extends Bundle {
     val x = UInt(3.W)
     val y = UInt(3.W)
   }

8.  type ClonePorts = internal.BaseModule.ClonePorts

   A record containing the results of CloneModuleAsRecord The apply method is retrieves the element with the supplied name.

9.  type Direction = ActualDirection
10.  case class DoubleParam(value: Double) extends Param with Product with Serializable
11.  abstract class ExtModule extends BaseBlackBox

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

    A variant of BlackBox, this has a more consistent naming scheme in allowing multiple top-level IO and does not drop the top prefix.

    Example:

    1. Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

       IBUFDS #(.DIFF_TERM("TRUE"),
                .IOSTANDARD("DEFAULT")) ibufds (
        .IB(ibufds_IB),
        .I(ibufds_I),
        .O(ibufds_O)
       );

       To instantiate it, a BlackBox can be used like following:

       import chisel3._
       import chisel3.experimental._
       
       // Example with Xilinx differential buffer IBUFDS
       class IBUFDS extends ExtModule(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                          "IOSTANDARD" -> "DEFAULT"
                            )) {
         val O = IO(Output(Clock()))
         val I = IO(Input(Clock()))
         val IB = IO(Input(Clock()))
       }

    Note

    The parameters API is experimental and may change

12.  final class HWTuple10[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data, +H <: Data, +I <: Data, +J <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple9

    Data equivalent of Scala's scala.Tuple9

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple9 in chisel3.experimental.conversions

13.  final class HWTuple2[+A <: Data, +B <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple2

    Data equivalent of Scala's scala.Tuple2

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple2 in chisel3.experimental.conversions

14.  final class HWTuple3[+A <: Data, +B <: Data, +C <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple3

    Data equivalent of Scala's scala.Tuple3

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple3 in chisel3.experimental.conversions

15.  final class HWTuple4[+A <: Data, +B <: Data, +C <: Data, +D <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple4

    Data equivalent of Scala's scala.Tuple4

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple4 in chisel3.experimental.conversions

16.  final class HWTuple5[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple5

    Data equivalent of Scala's scala.Tuple5

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple5 in chisel3.experimental.conversions

17.  final class HWTuple6[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple6

    Data equivalent of Scala's scala.Tuple6

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple6 in chisel3.experimental.conversions

18.  final class HWTuple7[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple7

    Data equivalent of Scala's scala.Tuple7

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple7 in chisel3.experimental.conversions

19.  final class HWTuple8[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data, +H <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple8

    Data equivalent of Scala's scala.Tuple8

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple8 in chisel3.experimental.conversions

20.  final class HWTuple9[+A <: Data, +B <: Data, +C <: Data, +D <: Data, +E <: Data, +F <: Data, +G <: Data, +H <: Data, +I <: Data] extends Bundle

    Data equivalent of Scala's scala.Tuple9

    Data equivalent of Scala's scala.Tuple9

    Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple9 in chisel3.experimental.conversions

21.  trait HasAutoTypename extends AnyRef

    Trait for Records that signals the compiler plugin to generate a typeName for the inheriting Record based on the parameter values provided to its constructor.

    Trait for Records that signals the compiler plugin to generate a typeName for the inheriting Record based on the parameter values provided to its constructor.

    Example:

    1. Consider a Bundle which manually implements typeName:

       class MyBundle(param1: Int, param2: Int)(gen: Data) extends Bundle {
         val foo = UInt(param1.W)
         val bar = UInt(param2.W)
         val data = gen
         override def typeName = s"MyBundle_${param1}_${param2}_${gen.typeName}"
       }
       
       (new MyBundle(3, 4)(SInt(3.W))).typeName // "MyBundle_3_4_SInt3"
       (new MyBundle(1, 32)(Bool())).typeName   // "MyBundle_1_32_Bool"

       An identical typeName implementation can be generated and provided with HasAutoTypename, making the manual implementation unnecessary:

       class MyBundle(param1: Int, param2: Int)(gen: Data) extends Bundle with HasAutoTypename {
         val foo = UInt(param1.W)
         val bar = UInt(param2.W)
         val data = gen
       }
       
       (new MyBundle(3, 4)(SInt(3.W))).typeName // "MyBundle_3_4_SInt3"
       (new MyBundle(1, 32)(Bool())).typeName   // "MyBundle_1_32_Bool"

22.  trait HasTypeAlias extends AnyRef
23.  case class IntParam(value: BigInt) extends Param with Product with Serializable
24.  abstract class IntrinsicModule extends BaseIntrinsicModule
25.  sealed trait NoSourceInfo extends SourceInfo
26.  trait OpaqueType extends Data

    Indicates if this Record represents an "Opaque Type"

    Indicates if this Record represents an "Opaque Type"

    Opaque types provide a mechanism for user-defined types that do not impose any "boxing" overhead in the emitted FIRRTL and Verilog. You can think about an opaque type Record as a box around a single element that only exists at Chisel elaboration time. Put another way, if this trait is mixed into a Record, the Record may only contain a single element with an empty name and there will be no _ in the name for that element in the emitted Verilog.

    See also

    OpaqueTypeSpec in Chisel's tests for example usage and expected output

27.  sealed abstract class Param extends AnyRef

    Parameters for BlackBoxes

28.  case class RawParam(value: String) extends Param with Product with Serializable

    Unquoted String

29.  case class RecordAlias extends Product with Serializable

    Wrapper object for a Record alias name.

    Wrapper object for a Record alias name. Primarily intended to provide an invocation point for source line locators, but also contains pertinent information to generating FIRRTL alias statements.

30.  trait SerializableModule[T <: SerializableModuleParameter] extends AnyRef

    Mixin this trait to let chisel auto serialize module, it has these constraints: 1.

    Mixin this trait to let chisel auto serialize module, it has these constraints: 1. Module should not be any inner class of other class, since serializing outer class is impossible. 2. Module should have and only have one parameter with type T:

    class FooSerializableModule[FooSerializableModuleParameter](val parameter: FooSerializableModuleParameter)

    3. user should guarantee the module is reproducible on their own.

31.  case class SerializableModuleGenerator[M <: SerializableModule[P], P <: SerializableModuleParameter](generator: Class[M], parameter: P)(implicit pTag: scala.reflect.api.JavaUniverse.TypeTag[P], mTag: scala.reflect.api.JavaUniverse.TypeTag[M]) extends Product with Serializable

    the serializable module generator:

    the serializable module generator:

    generator

    a non-inner class of module, which should be a subclass of SerializableModule

    parameter

    the parameter of generator

32.  trait SerializableModuleParameter extends AnyRef

    Parameter for SerializableModule, it should be serializable via upickle API.

    Parameter for SerializableModule, it should be serializable via upickle API. For more information, please refer to https://com-lihaoyi.github.io/upickle/

33.  sealed trait SourceInfo extends AnyRef

    Abstract base class for generalized source information.

34.  case class SourceLine(filename: String, line: Int, col: Int) extends SourceInfo with Product with Serializable

    For FIRRTL lines from a Scala source line.

    For FIRRTL lines from a Scala source line.

    Note

    A column == 0 indicates no column

35.  case class StringParam(value: String) extends Param with Product with Serializable
36.  class VecLiteralException extends ChiselException
37.  macro class dump extends internal.naming.dump

    Annotations

    @compileTimeOnly("macro annotation could not be expanded (since these are experimental, you must enable them with -Ymacro-annotations)")

38.  macro class treedump extends internal.naming.treedump

    Annotations

    @compileTimeOnly("macro annotation could not be expanded (since these are experimental, you must enable them with -Ymacro-annotations)")