Packages

final class Analog extends Element

Data type for representing bidirectional bitvectors of a given width

Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout) pins. There is currently no support for reading or writing of Analog types within Chisel code.

Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no effect.

Analog types are generally connected using the bidirectional attach mechanism, but also support limited bulkconnect <>. Analog types are only allowed to be bulk connected *once* in a given module. This is to prevent any surprising consequences of last connect semantics.

Source
Analog.scala
Note

This API is experimental and subject to change

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Element, Data, DataIntf, SourceInfoDoc, NamedComponent, HasId, InstanceId, AnyRef, Any
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  1. Analog
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  6. NamedComponent
  7. HasId
  8. InstanceId
  9. AnyRef
  10. Any
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  1. by AsReadOnly
  2. by DataEquality
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  4. by ConnectableDefault
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connection

  1. final def :#=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    producer

    the right-hand-side of the connection, all members will be driving, none will be driven-to

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  2. final def :#=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    producer

    the right-hand-side of the connection, all members will be driving, none will be driven-to

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  3. final def :#=[S <: Data](lProducer: => S)(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "mono-direction connection operator", aka the "coercion operator".

    The "mono-direction connection operator", aka the "coercion operator".

    For consumer :#= producer, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)

    Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '#' means to ignore flips, always drive from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes: - Connecting two util.DecoupledIO's would connect bits, valid, AND ready from producer to consumer (despite ready being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  4. final def :<=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    producer

    the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  5. final def :<=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    producer

    the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  6. final def :<=[S <: Data](lProducer: => S)(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "aligned connection operator" between a producer and consumer.

    The "aligned connection operator" between a producer and consumer.

    For consumer :<= producer, each of consumer's leaf members which are aligned with respect to consumer are driven from the corresponding producer leaf member. Only consumer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect bits and valid from producer to consumer, but leave ready unconnected
    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  7. final def :<>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    producer

    the right-hand-side of the connection

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  8. final def :<>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    producer

    the right-hand-side of the connection

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  9. final def :<>=[S <: Data](lProducer: => S)(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    The "bi-direction connection operator", aka the "tur-duck-en operator"

    For consumer :<>= producer, both producer and consumer leafs could be driving or be driven-to. The consumer's members aligned w.r.t. consumer will be driven by corresponding members of producer; the producer's members flipped w.r.t. producer will be driven by corresponding members of consumer

    Identical to calling :<= and :>= in sequence (order is irrelevant), e.g. consumer :<= producer then consumer :>= producer

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '<' means to connect from producer to consumer
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs. - An additional type restriction is that all relative orientations of consumer and producer must match exactly.

    Additional notes:

    • Connecting two wires of util.DecoupledIO chisel type would connect bits and valid from producer to consumer, and ready from consumer to producer.
    • If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
    • "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken; :<>= is a := stuffed with a <>
    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  10. final def :=(that: => Data)(implicit sourceInfo: SourceInfo): Unit

    The "strong connect" operator.

    The "strong connect" operator.

    For chisel3._, this operator is mono-directioned; all sub-elements of this will be driven by sub-elements of that.

    • Equivalent to this :#= that

    For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=

    • Equivalent to this :<>= that
    that

    the Data to connect from

    Definition Classes
    Data
  11. final def :>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    producer

    the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  12. final def :>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    producer

    the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")

    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  13. final def :>=[S <: Data](lProducer: => S)(implicit evidence: =:=[Analog, S], sourceInfo: SourceInfo): Unit

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.

    For consumer :>= producer, each of producer's leaf members which are flipped with respect to producer are driven from the corresponding consumer leaf member Only producer's leaf/branch alignments influence the connection.

    Symbol reference:

    • ':' is the consumer side
    • '=' is the producer side
    • '>' means to connect from consumer to producer

    The following restrictions apply:

    • The Chisel type of consumer and producer must be the "same shape" recursively:
      • All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
      • All vector types are the same length
      • All bundle types have the same member names, but the flips of members can be different between producer and consumer
    • The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.

    Additional notes:

    • Connecting two util.DecoupledIO's would connect ready from consumer to producer, but leave bits and valid unconnected
    Implicit
    This member is added by an implicit conversion from Analog toConnectableDefault[Analog] performed by method ConnectableDefault in chisel3.Data.
    Definition Classes
    ConnectableOpExtension
  14. final def <>(that: => Data)(implicit sourceInfo: SourceInfo): Unit

    The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

    The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

    For chisel3._, uses the chisel3.internal.BiConnect algorithm; sub-elements of that may end up driving sub-elements of this

    • Complicated semantics, hard to write quickly, will likely be deprecated in the future

    For Chisel._, emits the FIRRTL.<- operator

    • Equivalent to this :<>= that without the restrictions that bundle field names and vector sizes must match
    that

    the Data to connect from

    Definition Classes
    Data

Ungrouped

  1. def ===(rhs: Analog): Bool

    Dynamic recursive equality operator for generic Data

    Dynamic recursive equality operator for generic Data

    rhs

    a hardware Data to compare lhs to

    returns

    a hardware Bool asserted if lhs is equal to rhs

    Implicit
    This member is added by an implicit conversion from Analog toDataEquality[Analog] performed by method DataEquality in chisel3.Data.
    Definition Classes
    DataEquality
    Exceptions thrown

    ChiselException when lhs and rhs are different types during elaboration time

  2. def as[S <: Data](implicit ev: <:<[Analog, S]): connectable.Connectable[S]

    Static cast to a super type

    Static cast to a super type

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  3. macro def asTypeOf[T <: Data](that: T): T

    Does a reinterpret cast of the bits in this node into the format that provides.

    Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.

    x.asTypeOf(that) performs the inverse operation of x := that.toBits.

    Definition Classes
    DataIntf
    Note

    bit widths are NOT checked, may pad or drop bits from input

    ,

    that should have known widths

  4. final macro def asUInt: UInt

    Reinterpret cast to UInt.

    Reinterpret cast to UInt.

    Definition Classes
    DataIntf
    Note

    value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7

    ,

    Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.

  5. def autoSeed(name: String): Analog.this.type

    Takes the last seed suggested.

    Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).

    If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.

    Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.

    returns

    this object

    Definition Classes
    Data → HasId
  6. val base: Analog
    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  7. def cloneType: Analog.this.type

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

    cloneType must be defined for any Chisel object extending Data. It is responsible for constructing a basic copy of the object being cloned.

    returns

    a copy of the object.

    Definition Classes
    Analog → Data
  8. def containsAFlipped: Boolean
    Definition Classes
    Element → Data
  9. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  10. def exclude(members: (Analog) => Data*): connectable.Connectable[Analog]

    Select members of base to exclude

    Select members of base to exclude

    members

    functions given the base return a member to exclude

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  11. def exclude: connectable.Connectable[Analog]

    Adds base to excludes

    Adds base to excludes

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  12. def excludeAs[S <: Data](members: (Analog) => Data*)(implicit ev: <:<[Analog, S]): connectable.Connectable[S]

    Select members of base to exclude and static cast to a new type

    Select members of base to exclude and static cast to a new type

    members

    functions given the base return a member to exclude

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  13. def excludeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[Analog, S]): connectable.Connectable[S]

    Programmatically select members of base to exclude and static cast to a new type

    Programmatically select members of base to exclude and static cast to a new type

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  14. def excludeProbes: connectable.Connectable[Analog]

    Exclude probes

    Exclude probes

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  15. final def getWidth: Int

    Returns the width, in bits, if currently known.

    Returns the width, in bits, if currently known.

    Definition Classes
    Data
  16. def hasSeed: Boolean

    returns

    Whether either autoName or suggestName has been called

    Definition Classes
    HasId
  17. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  18. def instanceName: String
    Definition Classes
    HasId → InstanceId
  19. def isLit: Boolean
    Definition Classes
    Data
  20. final def isWidthKnown: Boolean

    Returns whether the width is currently known.

    Returns whether the width is currently known.

    Definition Classes
    Data
  21. def litOption: Option[BigInt]

    If this is a literal that is representable as bits, returns the value as a BigInt.

    If this is a literal that is representable as bits, returns the value as a BigInt. If not a literal, or not representable as bits (for example, is or contains Analog), returns None.

    Definition Classes
    Analog → Element → Data
  22. def litValue: BigInt

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

    Definition Classes
    Data
  23. def name: String
    Definition Classes
    Element
  24. def notWaivedOrSqueezedOrExcluded: Boolean

    True if no members are waived or squeezed or excluded

    True if no members are waived or squeezed or excluded

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  25. def parentModName: String
    Definition Classes
    HasId → InstanceId
  26. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  27. def pathName: String
    Definition Classes
    HasId → InstanceId
  28. def readOnly(implicit sourceInfo: SourceInfo): Analog

    Returns a read-only view of this Data

    Returns a read-only view of this Data

    It is illegal to connect to the return value of this method. This Data this method is called on must be a hardware type.

    Implicit
    This member is added by an implicit conversion from Analog toAsReadOnly[Analog] performed by method AsReadOnly in chisel3.Data.
    Definition Classes
    AsReadOnly
  29. def squeeze(members: (Analog) => Data*): connectable.Connectable[Analog]

    Select members of base to squeeze

    Select members of base to squeeze

    members

    functions given the base return a member to squeeze

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  30. def squeeze: connectable.Connectable[Analog]

    Adds base to squeezes

    Adds base to squeezes

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  31. def squeezeAll: connectable.Connectable[Analog]

    Squeeze all members of base

    Squeeze all members of base

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  32. def squeezeAllAs[S <: Data](implicit ev: <:<[Analog, S]): connectable.Connectable[S]

    Squeeze all members of base and upcast to super type

    Squeeze all members of base and upcast to super type

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  33. def squeezeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]]): connectable.Connectable[Analog]

    Programmatically select members of base to squeeze

    Programmatically select members of base to squeeze

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  34. def suggestName(seed: => String): Analog.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

    seed

    The seed for the name of this component

    returns

    this object

    Definition Classes
    HasId
  35. final def toAbsoluteTarget: ReferenceTarget

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Definition Classes
    NamedComponent → InstanceId
  36. final def toNamed: ComponentName

    Returns a FIRRTL ComponentName that references this object

    Returns a FIRRTL ComponentName that references this object

    Definition Classes
    NamedComponent → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  37. def toPrintable: Printable

    Default pretty printing

    Default pretty printing

    Definition Classes
    Analog → Data
  38. final def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    NamedComponent
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The NamedComponent must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  39. final def toRelativeTargetToHierarchy(root: Option[Hierarchy[BaseModule]]): ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    NamedComponent
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The NamedComponent must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  40. def toString(): String
    Definition Classes
    Analog → AnyRef → Any
  41. final def toTarget: ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object

    Returns a FIRRTL ReferenceTarget that references this object

    Definition Classes
    NamedComponent → InstanceId
    Note

    Should not be called until circuit elaboration is complete

  42. def typeName: String

    A stable typeName for this Analog

    A stable typeName for this Analog

    Definition Classes
    Analog → Data
  43. def unsafe: connectable.Connectable[Data]

    Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members

    Connect to/from all fields regardless of Scala type, squeeze if necessary, and don't error if mismatched members

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  44. def waive(members: (Analog) => Data*): connectable.Connectable[Analog]

    Select members of base to waive

    Select members of base to waive

    members

    functions given the base return a member to waive

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  45. def waiveAll: connectable.Connectable[Analog]

    Waive all members of base

    Waive all members of base

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  46. def waiveAllAs[S <: Data](implicit ev: <:<[Analog, S]): connectable.Connectable[S]

    Waive all members of base and static cast to a new type

    Waive all members of base and static cast to a new type

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  47. def waiveAs[S <: Data](members: (Analog) => Data*)(implicit ev: <:<[Analog, S]): connectable.Connectable[S]

    Select members of base to waive and static cast to a new type

    Select members of base to waive and static cast to a new type

    members

    functions given the base return a member to waive

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  48. def waiveEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[Analog, S]): connectable.Connectable[S]

    Programmatically select members of base to waive and static cast to a new type

    Programmatically select members of base to waive and static cast to a new type

    Implicit
    This member is added by an implicit conversion from Analog toConnectable[Analog] performed by method toConnectableDefault in chisel3.Data.
    Definition Classes
    Connectable
  49. def widthKnown: Boolean
    Definition Classes
    Element
  50. final def widthOption: Option[Int]

    Returns Some(width) if the width is known, else None.

    Returns Some(width) if the width is known, else None.

    Definition Classes
    Data

SourceInfoTransformMacro

These internal methods are not part of the public-facing API!

The equivalent public-facing methods do not have the do_ prefix or have the same name. Use and look at the documentation for those. If you want left shift, use <<, not do_<<. If you want conversion to a Seq of Bools look at the asBools above, not the one below. Users can safely ignore every method in this group!

🐉🐉🐉 Here be dragons... 🐉🐉🐉

These do_X methods are used to enable both implicit passing of SourceInfo while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your designs, are converted to their "hidden", do_*, via macro transformations. Without using macros here, only one of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a chained apply as an explicit 'implicit' argument and will throw type errors.

The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method into a call to an internal, hidden do_* that takes an explicit SourceInfo by inserting an implicitly[SourceInfo] as the explicit argument.

  1. def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo): T

    Definition Classes
    DataIntf
  2. def do_asUInt(implicit sourceInfo: SourceInfo): UInt

    Definition Classes
    DataIntf