Packages

  • package root

    This is the documentation for Chisel.

    This is the documentation for Chisel.

    Package structure

    The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

    The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

    Utility objects and methods are found in the util package.

    The testers package defines the basic interface for chisel testers.

    Definition Classes
    root
  • package chisel3

    This package contains the main chisel3 API.

    This package contains the main chisel3 API.

    Definition Classes
    root
  • package experimental

    Package for experimental features, which may have their API changed, be removed, etc.

    Package for experimental features, which may have their API changed, be removed, etc.

    Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.

    Definition Classes
    chisel3
  • package inlinetest
    Definition Classes
    experimental
  • HasTests
  • TestHarness
  • TestHarnessGenerator
  • TestHarnessWithResult
  • TestParameters
  • TestResultBundle

abstract class TestHarness[M <: RawModule, R] extends FixedIOModule[TestResultBundle] with Public

TestHarnesses for inline tests should extend this. This abstract class sets the correct desiredName for the module, instantiates the DUT, and provides methods to generate the test. The resetType matches that of the DUT, or is Synchronous if it must be inferred (this can be overriden).

A TestHarness has the following ports:

- clock: shall be driven at a constant frequency by the simulation. - reset: shall be asserted for one cycle from the first positive edge of clock by the simulation. - reset: shall be asserted for one cycle from the first positive edge of clock by the simulation. - finish: the test shall be considered complete on the first positive edge of finish.

M

the type of the DUT module

R

the type of the result returned by the test body

Source
InlineTest.scala
Known Subclasses
Type Hierarchy
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. TestHarness
  2. Public
  3. FixedIOModule
  4. FixedIOBaseModule
  5. Module
  6. ImplicitReset
  7. ImplicitClock
  8. RawModule
  9. BaseModule
  10. IsInstantiable
  11. HasId
  12. InstanceId
  13. AnyRef
  14. Any
Implicitly
  1. by BaseModuleExtensions
  2. by IsInstantiableExtensions
  3. by any2stringadd
  4. by StringFormat
  5. by Ensuring
  6. by ArrowAssoc
  1. Hide All
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new TestHarness(test: TestParameters[M, R])

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. def +(other: String): String
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toany2stringadd[TestHarness[M, R]] performed by method any2stringadd in scala.Predef.
    Definition Classes
    any2stringadd
  4. def ->[B](y: B): (TestHarness[M, R], B)
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toArrowAssoc[TestHarness[M, R]] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @inline()
  5. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  6. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T

    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef must be a chisel type and not be bound to hardware.

    Also registers an Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.

    Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

    Attributes
    protected
    Definition Classes
    BaseModule
  8. val _body: Block
    Attributes
    protected
    Definition Classes
    BaseModule
  9. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  10. def _moduleDefinitionIdentifierProposal: String
    Attributes
    protected
    Definition Classes
    BaseModule
  11. def _sourceInfo: SourceInfo
    Attributes
    protected
    Definition Classes
    BaseModule
  12. def _traitModuleDefinitionIdentifierProposal: Option[String]
    Attributes
    protected
    Definition Classes
    BaseModule
  13. def afterModuleBuilt(gen: => Unit): Unit

    Hook to invoke hardware generators after a Module has been constructed and closed.

    Hook to invoke hardware generators after a Module has been constructed and closed.

    This is useful for running hardware generators after a Module's constructor has run and its Definition is available, while still having access to arguments and definitions in the constructor. The Module itself can no longer be modified at this point.

    An interesting application of this is the generation of unit tests whenever a module is instantiated. For example:

    class Example(N: int) extends RawModule {
      private val someSecret: Int = ...
    
      afterModuleBuilt {
        // Executes once the surrounding module is closed.
        // We can get its definition at this point and pass it to another module.
        Definition(ExampleTest(this.definition, someSecret))
      }
    }
    
    class ExampleTest(unitDef: Definition[Example], someSecret: Int) extends RawModule {
      // Instantiate the generated module and test it.
      val unit = Instance(unitDef)
      ...
    }
    
    class Parent extends RawModule {
      Instantiate(Example(42))
    }
    
    // Resulting modules:
    // - Parent (top-level)
    //   - instantiates Example
    // - ExampleTest (top-level)
    //   - instantiates Example
    // - Example
    Attributes
    protected
    Definition Classes
    RawModule
  14. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  15. def atModuleBodyEnd(gen: => Unit): Unit

    Hook to invoke hardware generators after the rest of the Module is constructed.

    Hook to invoke hardware generators after the rest of the Module is constructed.

    This is a power-user API, and should not normally be needed.

    In rare cases, it is necessary to run hardware generators at a late stage, but still within the scope of the Module. In these situations, atModuleBodyEnd may be used to register such generators. For example:

    class Example extends RawModule {
      atModuleBodyEnd {
        val extraPort0 = IO(Output(Bool()))
        extraPort0 := 0.B
      }
    }

    Any generators registered with atModuleBodyEnd are the last code to execute when the Module is constructed. The execution order is:

    • The constructors of any super classes or traits the Module extends
    • The constructor of the Module itself
    • The atModuleBodyEnd generators

    The atModuleBodyEnd generators execute in the lexical order they appear in the Module constructor.

    For example:

    trait Parent {
      // Executes first.
      val foo = ...
    }
    
    class Example extends Parent {
      // Executes second.
      val bar = ...
    
      atModuleBodyEnd {
        // Executes fourth.
        val qux = ...
      }
    
      atModuleBodyEnd {
        // Executes fifth.
        val quux = ...
      }
    
      // Executes third..
      val baz = ...
    }

    If atModuleBodyEnd is used in a Definition, any generated hardware will be included in the Definition. However, it is currently not possible to annotate any val within atModuleBodyEnd as @public.

    Attributes
    protected
    Definition Classes
    RawModule
  16. final val clock: Clock
    Definition Classes
    Module
  17. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native()
  18. final val definitionIdentifier: String

    Represents an eagerly-determined unique and descriptive identifier for this module

    Represents an eagerly-determined unique and descriptive identifier for this module

    Definition Classes
    BaseModule
  19. final def desiredName: String

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The desired name of this module (which will be used in generated FIRRTL IR or Verilog).

    The name of a module approximates the behavior of the Java Reflection getSimpleName method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:

    - Anonymous modules will get an "_Anon" tag - Modules defined in functions will use their class name and not a numeric name

    Definition Classes
    TestHarnessBaseModule
    Note

    If you want a custom or parametric name, override this method.

  20. final val dut: Instance[M]
    Attributes
    protected
  21. def endIOCreation()(implicit si: SourceInfo): Unit

    Disallow any more IO creation for this module.

    Disallow any more IO creation for this module.

    Definition Classes
    BaseModule
  22. def ensuring(cond: (TestHarness[M, R]) => Boolean, msg: => Any): TestHarness[M, R]
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toEnsuring[TestHarness[M, R]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  23. def ensuring(cond: (TestHarness[M, R]) => Boolean): TestHarness[M, R]
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toEnsuring[TestHarness[M, R]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  24. def ensuring(cond: Boolean, msg: => Any): TestHarness[M, R]
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toEnsuring[TestHarness[M, R]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  25. def ensuring(cond: Boolean): TestHarness[M, R]
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toEnsuring[TestHarness[M, R]] performed by method Ensuring in scala.Predef.
    Definition Classes
    Ensuring
  26. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  27. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  28. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable])
  29. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  30. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  31. def getInstantiatingBlock: Option[Block]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  32. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  33. def hasBody: Boolean
    Attributes
    protected
    Definition Classes
    RawModuleBaseModule
  34. def hasSeed: Boolean

    returns

    Whether either autoName or suggestName has been called

    Definition Classes
    HasId
  35. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  36. def implicitClock: Clock

    Method that should point to the user-defined Clock

    Method that should point to the user-defined Clock

    Attributes
    protected
    Definition Classes
    ModuleImplicitClock
  37. def implicitReset: Reset

    Method that should point to the user-defined Reset

    Method that should point to the user-defined Reset

    Attributes
    protected
    Definition Classes
    ModuleImplicitReset
  38. def instanceName: String

    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  39. final val io: TestResultBundle
    Definition Classes
    FixedIOBaseModule
    Annotations
    @public()
  40. final val ioGenerator: TestResultBundle

    A generator of IO

    A generator of IO

    Definition Classes
    FixedIOModuleFixedIOBaseModule
  41. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  42. def isPublic: Boolean

    Is this module public?

    Is this module public?

    Users can override this if they need more control over when outputs of this Module should be considered public

    Definition Classes
    Public
  43. def localModulePrefix: Option[String]

    Additional module prefix, applies to this module if defined (unless localModulePrefixAppliesToSelf is false) and all children.

    Additional module prefix, applies to this module if defined (unless localModulePrefixAppliesToSelf is false) and all children.

    Definition Classes
    BaseModule
  44. def localModulePrefixAppliesToSelf: Boolean

    Should localModulePrefix apply to this module? Defaults to true.

    Should localModulePrefix apply to this module? Defaults to true.

    Users should override to false if localModulePrefix should apply only to children.

    Definition Classes
    BaseModule
  45. def localModulePrefixUseSeparator: Boolean

    Should the localModulePrefix include a separator between prefix and the Module name

    Should the localModulePrefix include a separator between prefix and the Module name

    Defaults to true, users can override to false if they don't want a separator.

    Definition Classes
    BaseModule
  46. def moduleBuilt(): Unit

    Called once the module's definition has been fully built.

    Called once the module's definition has been fully built. At this point the module can be instantiated through its definition.

    Attributes
    protected[chisel3]
    Definition Classes
    RawModuleBaseModule
  47. final val modulePrefix: String

    The resolved module prefix used for this Module.

    The resolved module prefix used for this Module.

    Includes localModulePrefix if defined and if localModulePrefixAppliesToSelf is true.

    Definition Classes
    BaseModule
  48. final lazy val name: String

    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  49. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  50. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  51. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  52. def parentModName: String
    Definition Classes
    HasId → InstanceId
  53. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  54. def pathName: String
    Definition Classes
    HasId → InstanceId
  55. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  56. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  57. final val reset: Reset
    Definition Classes
    Module
  58. final def resetType: Type

    Override this to explicitly set the type of reset you want on this module , before any reset inference

    Override this to explicitly set the type of reset you want on this module , before any reset inference

    Definition Classes
    TestHarnessModule
  59. def suggestName(seed: => String): TestHarness.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

    seed

    The seed for the name of this component

    returns

    this object

    Definition Classes
    HasId
  60. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  61. final val testResult: R
    Attributes
    protected
  62. final def toAbsoluteTarget: IsModule

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  63. def toDefinition: Definition[TestHarness[M, R]]
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toBaseModuleExtensions[TestHarness[M, R]] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
    Definition Classes
    BaseModuleExtensions
  64. final def toNamed: ModuleName

    Returns a FIRRTL ModuleName that references this object

    Returns a FIRRTL ModuleName that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  65. final def toRelativeTarget(root: Option[BaseModule]): IsModule

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    BaseModule
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The BaseModule must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  66. final def toRelativeTargetToHierarchy(root: Option[Hierarchy[BaseModule]]): IsModule

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

    If root is defined, the target is a hierarchical path starting from root.

    If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

    Definition Classes
    BaseModule
    Note

    If root is defined, and has not finished elaboration, this must be called within atModuleBodyEnd.

    ,

    The BaseModule must be a descendant of root, if it is defined.

    ,

    This doesn't have special handling for Views.

  67. def toString(): String
    Definition Classes
    AnyRef → Any
  68. final def toTarget: ModuleTarget

    Returns a FIRRTL ModuleTarget that references this object

    Returns a FIRRTL ModuleTarget that references this object

    Definition Classes
    BaseModuleInstanceId
    Note

    Should not be called until circuit elaboration is complete

  69. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  70. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  71. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()

Shadowed Implicit Value Members

  1. def toInstance: Instance[TestHarness[M, R]]
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toBaseModuleExtensions[TestHarness[M, R]] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
    Shadowing
    This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
    To access this member you can use a type ascription:
    (testHarness: BaseModuleExtensions[TestHarness[M, R]]).toInstance
    Definition Classes
    BaseModuleExtensions

Deprecated Value Members

  1. def formatted(fmtstr: String): String
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toStringFormat[TestHarness[M, R]] performed by method StringFormat in scala.Predef.
    Definition Classes
    StringFormat
    Annotations
    @deprecated @inline()
    Deprecated

    (Since version 2.12.16) Use formatString.format(value) instead of value.formatted(formatString), or use the f"" string interpolator. In Java 15 and later, formatted resolves to the new method in String which has reversed parameters.

  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  6. def toInstance: Instance[TestHarness[M, R]]
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toIsInstantiableExtensions[TestHarness[M, R]] performed by method IsInstantiableExtensions in chisel3.experimental.hierarchy.core.IsInstantiable.
    Shadowing
    This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
    To access this member you can use a type ascription:
    (testHarness: IsInstantiableExtensions[TestHarness[M, R]]).toInstance
    Definition Classes
    IsInstantiableExtensions
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 7.0.0) Use of @instantiable on user-defined types is deprecated. Implement Lookupable for your type instead.

  7. def [B](y: B): (TestHarness[M, R], B)
    Implicit
    This member is added by an implicit conversion from TestHarness[M, R] toArrowAssoc[TestHarness[M, R]] performed by method ArrowAssoc in scala.Predef.
    Definition Classes
    ArrowAssoc
    Annotations
    @deprecated
    Deprecated

    (Since version 2.13.0) Use -> instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.

Inherited from Public

Inherited from Module

Inherited from ImplicitReset

Inherited from ImplicitClock

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Inherited by implicit conversion BaseModuleExtensions fromTestHarness[M, R] to BaseModuleExtensions[TestHarness[M, R]]

Inherited by implicit conversion IsInstantiableExtensions fromTestHarness[M, R] to IsInstantiableExtensions[TestHarness[M, R]]

Inherited by implicit conversion any2stringadd fromTestHarness[M, R] to any2stringadd[TestHarness[M, R]]

Inherited by implicit conversion StringFormat fromTestHarness[M, R] to StringFormat[TestHarness[M, R]]

Inherited by implicit conversion Ensuring fromTestHarness[M, R] to Ensuring[TestHarness[M, R]]

Inherited by implicit conversion ArrowAssoc fromTestHarness[M, R] to ArrowAssoc[TestHarness[M, R]]

Ungrouped