package stimulus
- Alphabetic
- Public
- Protected
Type Members
- trait ResetProcedure[A] extends Type[A]
Stimulus that will apply a standard reset procedure to a Chisel circuit.
Stimulus that will apply a standard reset procedure to a Chisel circuit.
The reset procedure is as follows:
time 0: bring everything up using simulator settings time 1: bring reset out of
x
and deassert it. time 2: assert reset time 3: first clock edge time 4 + n: deassert reset (where n ==additionalResetCycles
)This intentionally structured to guarantee the following properties:
- There is guaranteed to be a time when FIRRTL/Verilog-based
randomization can happen at _either_ time 0 or time 1.)
2. If time 1 is used for FIRRTL/Verilog-based randomization, then time 0
can be used for simulator-based initialization, e.g.,
+vcs+initreg+random
. Simulator initialization will race with FIRRTL/Verilog-based randomization and it is critical that they do not happen at the same time. 3. Both FIRRTL/Verilog-based randomization and simulator-based randomization should not occur on a clock edge, e.g., an edge when reset is asserted. This can be yet-another race condition that has to be avoided. 4. Reset always sees a posedge. This avoids problems with asynchronous reset logic behavior where they may (correctly in Verilog) _not_ fire if you bring the design with reset asserted. Note: it would be fine to do anx -> 1
transition to show an edge, however, it looks cleaner to bring reset to0
.
- There is guaranteed to be a time when FIRRTL/Verilog-based
randomization can happen at _either_ time 0 or time 1.)
2. If time 1 is used for FIRRTL/Verilog-based randomization, then time 0
can be used for simulator-based initialization, e.g.,
- trait RunUntilFinished[A] extends Type[A]
Stimulus that will run a simulation, expecting a chisel3.stop (a Verilog
$finish
) to occur before a maximum number of cycles has elapsed.Stimulus that will run a simulation, expecting a chisel3.stop (a Verilog
$finish
) to occur before a maximum number of cycles has elapsed.- See also
- trait RunUntilSuccess[A] extends Type[A]
Stimulus that will run a simulation expecting a "success" port to assert.
Stimulus that will run a simulation expecting a "success" port to assert.
If the specified "success" port does not assert, then an Exceptions.Timeout will be thrown.
- See also
Value Members
- object ResetProcedure
Factory of ResetProcedure stimulus.
- object RunUntilFinished
Factory of RunUntilFinished stimulus for different kinds of modules.
- object RunUntilSuccess
- object Stimulus
Types and utility functions related to the stimulus package.
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.