Value Members

1.  final def !=(arg0: Any): Boolean

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2.  final def ##: Int

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3.  final def ==(arg0: Any): Boolean

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4.  final def asInstanceOf[T0]: T0

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5.  def clone(): AnyRef

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   protected[lang]

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   @throws(classOf[java.lang.CloneNotSupportedException]) @native()

6.  def convert(gen: => RawModule, args: Array[String] = Array.empty): Circuit

   Return a CHIRRTL circuit for a Chisel module

   Return a CHIRRTL circuit for a Chisel module

   gen

   a call-by-name Chisel module

7.  def emitCHIRRTL(gen: => RawModule, args: Array[String] = Array.empty): String

   Elaborate a Chisel circuit into a CHIRRTL string

8.  def emitCHIRRTLFile(gen: => RawModule, args: Array[String] = Array.empty): AnnotationSeq

   Elaborates a Chisel circuit and emits it to a file

   Elaborates a Chisel circuit and emits it to a file

   gen

   a call-by-name Chisel module

   args

   additional command line arguments to pass to Chisel

9.  def emitFIRRTLDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

   Compile a Chisel circuit to FIRRTL dialect

10.  def emitHWDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

    Compile a Chisel circuit to HWS dialect

11.  def emitSystemVerilog(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

    Compile a Chisel circuit to SystemVerilog

    Compile a Chisel circuit to SystemVerilog

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel

    firtoolOpts

    additional circt.stage.FirtoolOption to pass to firtool

    returns

    a string containing the Verilog output

12.  def emitSystemVerilogFile(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): AnnotationSeq

    Compile a Chisel circuit to SystemVerilog with file output

    Compile a Chisel circuit to SystemVerilog with file output

    gen

    a call-by-name Chisel module

    args

    additional command line arguments to pass to Chisel

    firtoolOpts

    additional command line options to pass to firtool

    returns

    a string containing the Verilog output

13.  final def eq(arg0: AnyRef): Boolean

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14.  def equals(arg0: AnyRef): Boolean

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15.  def finalize(): Unit

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    protected[lang]

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    @throws(classOf[java.lang.Throwable])

16.  final def getClass(): Class[_ <: AnyRef]

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    @native()

17.  def hashCode(): Int

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    @native()

18.  final def isInstanceOf[T0]: Boolean

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19.  final def ne(arg0: AnyRef): Boolean

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20.  final def notify(): Unit

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    @native()

21.  final def notifyAll(): Unit

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    @native()

22.  final def synchronized[T0](arg0: => T0): T0

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23.  def toString(): String

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24.  final def wait(): Unit

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    @throws(classOf[java.lang.InterruptedException])

25.  final def wait(arg0: Long, arg1: Int): Unit

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    @throws(classOf[java.lang.InterruptedException])

26.  final def wait(arg0: Long): Unit

    Definition Classes

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    @throws(classOf[java.lang.InterruptedException]) @native()