object ChiselStage
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- def elaborate(gen: => RawModule, args: Array[String] = Array.empty): ElaboratedCircuit
Run elaboration and return the ElaboratedCircuit
Run elaboration and return the ElaboratedCircuit
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- returns
the ElaboratedCircuit
- def emitBtor2(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String
Compile a Chisel circuit to btor2
Compile a Chisel circuit to btor2
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- firtoolOpts
additional command line options to pass to firtool
- returns
a string containing the btor2 output
- def emitCHIRRTL(gen: => RawModule, args: Array[String] = Array.empty): String
Elaborate a Chisel circuit into a CHIRRTL string
- def emitCHIRRTLFile(gen: => RawModule, args: Array[String] = Array.empty): AnnotationSeq
Elaborates a Chisel circuit and emits it to a file
Elaborates a Chisel circuit and emits it to a file
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- def emitFIRRTLDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String
Compile a Chisel circuit to FIRRTL dialect
- def emitHWDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String
Compile a Chisel circuit to HWS dialect
- def emitSystemVerilog(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String
Compile a Chisel circuit to SystemVerilog
Compile a Chisel circuit to SystemVerilog
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- firtoolOpts
additional circt.stage.FirtoolOption to pass to firtool
- returns
a string containing the Verilog output
- def emitSystemVerilogFile(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): AnnotationSeq
Compile a Chisel circuit to multiple SystemVerilog files.
Compile a Chisel circuit to multiple SystemVerilog files.
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- firtoolOpts
additional command line options to pass to firtool
- returns
the annotations that exist after compilation
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Deprecated Value Members
- def convert(gen: => RawModule, args: Array[String] = Array.empty): Circuit
Return a CHIRRTL circuit for a Chisel module
Return a CHIRRTL circuit for a Chisel module
- gen
a call-by-name Chisel module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 6.8.0) Use elaborate or one of the emit* methods instead
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.