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svsim.Backend

HarnessCompilationFlags

object HarnessCompilationFlags

A namespace for flags affecting which code in the harness is compiled.

Source
Backend.scala
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  1. final def !=(arg0: Any): Boolean
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  2. final def ##: Int
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  6. val enableFsdbTracingSupport: String
  7. val enableFstTracingSupport: String
  8. val enableVCSSupport: String

    This flag controls if VCS-specifc code is compiled.

  9. val enableVcdTracingSupport: String

    Flags enabling various tracing mechanisms.

    Flags enabling various tracing mechanisms. Note: These flags do not cause tracing to occur, they simply support for these tracing mechanisms in the harness.

  10. val enableVerilatorSupport: String

    Verilator support requires that we manually implement some SystemVerilog functions, such as run_simulation and simulation_main.

    Verilator support requires that we manually implement some SystemVerilog functions, such as run_simulation and simulation_main. These flags control the Verilator-specific code paths.

  11. val enableVerilatorTrace: String
  12. val enableVpdTracingSupport: String
  13. final def eq(arg0: AnyRef): Boolean
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  21. final def notifyAll(): Unit
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  22. val supportsDelayInPublicFunctions: String

    Verilator does not currently support delay (#delay) in DPI functions, so we omit the SystemVerilog definition of the run_simulation function and instead provide a C implementation.

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