trait HasExtModuleInline extends ExtModule
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- ExtModule
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Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- def +(other: String): String
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toany2stringadd[HasExtModuleInline] performed by method any2stringadd in scala.Predef.
- Definition Classes
- any2stringadd
- def ->[B](y: B): (HasExtModuleInline, B)
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toArrowAssoc[HasExtModuleInline] performed by method ArrowAssoc in scala.Predef.
- Definition Classes
- ArrowAssoc
- Annotations
- @inline()
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
This must wrap the datatype used to set the io field of any Module.
This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])
Items in [] are optional.
The granted iodef must be a chisel type and not be bound to hardware.
Also registers an Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.
TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _moduleDefinitionIdentifierProposal: String
- Attributes
- protected
- Definition Classes
- BaseModule
- def _sourceInfo: SourceInfo
- Attributes
- protected
- Definition Classes
- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def circuitName: String
- Definition Classes
- HasId
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native()
- final val definitionIdentifier: String
Represents an eagerly-determined unique and descriptive identifier for this module
Represents an eagerly-determined unique and descriptive identifier for this module
- Definition Classes
- BaseModule
- def desiredName: String
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The name of a module approximates the behavior of the Java Reflection
getSimpleNamemethod https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:- Anonymous modules will get an
"_Anon"tag - Modules defined in functions will use their class name and not a numeric name- Definition Classes
- BaseModule
- Note
If you want a custom or parametric name, override this method.
- def endIOCreation()(implicit si: SourceInfo): Unit
Disallow any more IO creation for this module.
Disallow any more IO creation for this module.
- Definition Classes
- BaseModule
- def ensuring(cond: (HasExtModuleInline) => Boolean, msg: => Any): HasExtModuleInline
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toEnsuring[HasExtModuleInline] performed by method Ensuring in scala.Predef.
- Definition Classes
- Ensuring
- def ensuring(cond: (HasExtModuleInline) => Boolean): HasExtModuleInline
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toEnsuring[HasExtModuleInline] performed by method Ensuring in scala.Predef.
- Definition Classes
- Ensuring
- def ensuring(cond: Boolean, msg: => Any): HasExtModuleInline
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toEnsuring[HasExtModuleInline] performed by method Ensuring in scala.Predef.
- Definition Classes
- Ensuring
- def ensuring(cond: Boolean): HasExtModuleInline
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toEnsuring[HasExtModuleInline] performed by method Ensuring in scala.Predef.
- Definition Classes
- Ensuring
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable])
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
Signal name (for simulation).
Signal name (for simulation).
- Definition Classes
- BaseModule → HasId → InstanceId
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- final lazy val name: String
Legalized name of this module.
Legalized name of this module.
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
- val params: Map[String, Param]
- Definition Classes
- ExtModule
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- def setInline(blackBoxName: String, blackBoxInline: String): Unit
Creates a black box verilog file, from the contents of a local string
Creates a black box verilog file, from the contents of a local string
- blackBoxName
The black box module name, to create filename
- blackBoxInline
The black box contents
- def suggestName(seed: => String): HasExtModuleInline.this
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than
autoSeed, in that regardless of whetherautoSeedwas called, suggestName will always take precedence.- seed
The seed for the name of this component
- returns
this object
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- final def toAbsoluteTarget: IsModule
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- def toDefinition: Definition[HasExtModuleInline]
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toBaseModuleExtensions[HasExtModuleInline] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
- Definition Classes
- BaseModuleExtensions
- final def toNamed: ModuleName
Returns a FIRRTL ModuleName that references this object
Returns a FIRRTL ModuleName that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- final def toRelativeTarget(root: Option[BaseModule]): IsModule
Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.
Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.
If
rootis defined, the target is a hierarchical path starting fromroot.If
rootis not defined, the target is a hierarchical path equivalent totoAbsoluteTarget.- Definition Classes
- BaseModule
- Note
If
,rootis defined, and has not finished elaboration, this must be called withinatModuleBodyEnd.The BaseModule must be a descendant of
,root, if it is defined.This doesn't have special handling for Views.
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
Shadowed Implicit Value Members
- def toInstance: Instance[HasExtModuleInline]
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toBaseModuleExtensions[HasExtModuleInline] performed by method BaseModuleExtensions in chisel3.experimental.BaseModule.
- Shadowing
- This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
To access this member you can use a type ascription:(hasExtModuleInline: BaseModuleExtensions[HasExtModuleInline]).toInstance
- Definition Classes
- BaseModuleExtensions
- def toInstance: Instance[HasExtModuleInline]
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toIsInstantiableExtensions[HasExtModuleInline] performed by method IsInstantiableExtensions in chisel3.experimental.hierarchy.core.IsInstantiable.
- Shadowing
- This implicitly inherited member is ambiguous. One or more implicitly inherited members have similar signatures, so calling this member may produce an ambiguous implicit conversion compiler error.
To access this member you can use a type ascription:(hasExtModuleInline: IsInstantiableExtensions[HasExtModuleInline]).toInstance
- Definition Classes
- IsInstantiableExtensions
Deprecated Value Members
- def formatted(fmtstr: String): String
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toStringFormat[HasExtModuleInline] performed by method StringFormat in scala.Predef.
- Definition Classes
- StringFormat
- Annotations
- @deprecated @inline()
- Deprecated
(Since version 2.12.16) Use
formatString.format(value)instead ofvalue.formatted(formatString), or use thef""string interpolator. In Java 15 and later,formattedresolves to the new method in String which has reversed parameters.
- def →[B](y: B): (HasExtModuleInline, B)
- Implicit
- This member is added by an implicit conversion from HasExtModuleInline toArrowAssoc[HasExtModuleInline] performed by method ArrowAssoc in scala.Predef.
- Definition Classes
- ArrowAssoc
- Annotations
- @deprecated
- Deprecated
(Since version 2.13.0) Use
->instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.