object ShiftRegister
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- Reg.scala
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- macro def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T
Returns the n-cycle delayed version of the input signal with reset initialization.
Returns the n-cycle delayed version of the input signal with reset initialization.
- in
input to delay
- n
number of cycles to delay
- resetData
reset value for each register in the shift
- en
enable the shift
val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena)
Example: - macro def apply[T <: Data](in: T, n: Int): T
Returns the n-cycle delayed version of the input signal.
Returns the n-cycle delayed version of the input signal.
Enable is assumed to be true.
- in
input to delay
- n
number of cycles to delay
val regDelayTwo = ShiftRegister(nextVal, 2)
Example: - macro def apply[T <: Data](in: T, n: Int, en: Bool): T
Returns the n-cycle delayed version of the input signal.
Returns the n-cycle delayed version of the input signal.
- in
input to delay
- n
number of cycles to delay
- en
enable the shift
val regDelayTwo = ShiftRegister(nextVal, 2, ena)
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- def do_apply[T <: Data](in: T, n: Int, en: Bool = true.B)(implicit sourceInfo: SourceInfo): T
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- macro def mem[T <: Data](in: T, n: Int, en: Bool, useDualPortSram: Boolean, name: Option[String]): T
Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).
Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).
- in
input to delay
- n
number of cycles to delay
- en
enable the shift
- useDualPortSram
dual port or single port SRAM based implementation
- name
name of SyncReadMem object
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