o

chisel3.util

ShiftRegister

object ShiftRegister

Source
Reg.scala
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  1. final def !=(arg0: Any): Boolean
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  2. final def ##: Int
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  3. final def ==(arg0: Any): Boolean
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  4. macro def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T

    Returns the n-cycle delayed version of the input signal with reset initialization.

    Returns the n-cycle delayed version of the input signal with reset initialization.

    in

    input to delay

    n

    number of cycles to delay

    resetData

    reset value for each register in the shift

    en

    enable the shift

    Example:
    1. val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena)
  5. macro def apply[T <: Data](in: T, n: Int): T

    Returns the n-cycle delayed version of the input signal.

    Returns the n-cycle delayed version of the input signal.

    Enable is assumed to be true.

    in

    input to delay

    n

    number of cycles to delay

    Example:
    1. val regDelayTwo = ShiftRegister(nextVal, 2)
  6. macro def apply[T <: Data](in: T, n: Int, en: Bool): T

    Returns the n-cycle delayed version of the input signal.

    Returns the n-cycle delayed version of the input signal.

    in

    input to delay

    n

    number of cycles to delay

    en

    enable the shift

    Example:
    1. val regDelayTwo = ShiftRegister(nextVal, 2, ena)
  7. final def asInstanceOf[T0]: T0
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  8. def clone(): AnyRef
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    @throws(classOf[java.lang.CloneNotSupportedException]) @native()
  9. def do_apply[T <: Data](in: T, n: Int, resetData: T, en: Bool)(implicit sourceInfo: SourceInfo): T

  10. def do_apply[T <: Data](in: T, n: Int)(implicit sourceInfo: SourceInfo): T

  11. def do_apply[T <: Data](in: T, n: Int, en: Bool = true.B)(implicit sourceInfo: SourceInfo): T

  12. def do_mem[T <: Data](in: T, n: Int, en: Bool, useDualPortSram: Boolean, name: Option[String])(implicit sourceInfo: SourceInfo): T

  13. final def eq(arg0: AnyRef): Boolean
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  15. def finalize(): Unit
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  19. macro def mem[T <: Data](in: T, n: Int, en: Bool, useDualPortSram: Boolean, name: Option[String]): T

    Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).

    Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).

    in

    input to delay

    n

    number of cycles to delay

    en

    enable the shift

    useDualPortSram

    dual port or single port SRAM based implementation

    name

    name of SyncReadMem object

  20. final def ne(arg0: AnyRef): Boolean
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  21. final def notify(): Unit
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  23. final def synchronized[T0](arg0: => T0): T0
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  24. def toString(): String
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  25. final def wait(): Unit
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  26. final def wait(arg0: Long, arg1: Int): Unit
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  27. final def wait(arg0: Long): Unit
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